586 lines
21 KiB
C
586 lines
21 KiB
C
/*++
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Copyright (c) Microsoft Corporation. All rights reserved.
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Module Name:
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phy.h
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Abstract:
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Interface to Ethernet transceiver code inside the ROM
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Revision History:
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04/05/2001 davidx
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Created it.
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--*/
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#ifndef _PHY_H_
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#define _PHY_H_
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//
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// Initialize the PHY
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//
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NTKERNELAPI
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NTSTATUS
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PhyInitialize(
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BOOL forceReset,
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VOID* param OPTIONAL
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);
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//
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// Get the current link state
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//
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NTKERNELAPI
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DWORD
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PhyGetLinkState(
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BOOL update
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);
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#define BIT(n) (1u << (n))
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//
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// MII/PHY related declarations
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//
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#define MIIREG_CONTROL 0
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#define MIIREG_STATUS 1
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#define MIIREG_ANAR 4
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#define MIIREG_LPANAR 5
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#define MIICONTROL_RESET BIT(15)
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#define MIICONTROL_LOOPBACK_ENABLED BIT(14)
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#define MIICONTROL_SPEED_SELECTION_BIT1 BIT(13)
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#define MIICONTROL_ENABLE_AUTO_NEGOTIATION BIT(12)
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#define MIICONTROL_POWER_DOWN BIT(11)
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#define MIICONTROL_ELECTRICALLY_ISOLATE_PHY BIT(10)
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#define MIICONTROL_RESTART_AUTO_NEGOTIATION BIT(9)
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#define MIICONTROL_FULL_DUPLEX_MODE BIT(8)
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#define MIICONTROL_ENABLE_COLLISION_SIGNAL_TEST BIT(7)
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#define MIICONTROL_SPEED_SELECTION_BIT0 BIT(6)
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#define MIISTATUS_100MBS_T4_CAPABLE BIT(15)
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#define MIISTATUS_100MBS_X_FULL_DUPLEX_CAPABLE BIT(14)
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#define MIISTATUS_100MBS_X_HALF_DUPLEX_CAPABLE BIT(13)
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#define MIISTATUS_10MBS_FULL_DUPLEX_CAPABLE BIT(12)
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#define MIISTATUS_10MBS_HALF_DUPLEX_CAPABLE BIT(11)
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#define MIISTATUS_100MBS_T2_FULL_DUPLEX_CAPABLE BIT(10)
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#define MIISTATUS_100MBS_T2_HALF_DUPLEX_CAPABLE BIT(9)
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#define MIISTATUS_EXTENDED_STATUS_AVAILABLE BIT(8)
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#define MIISTATUS_PREAMBLE_SUPPRESSED_FRAME_OK BIT(6)
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#define MIISTATUS_AUTO_NEGOTIATION_COMPLETE BIT(5)
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#define MIISTATUS_REMOTE_FAULT_DETECTED BIT(4)
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#define MIISTATUS_AUTO_NEGOTIATION_CAPABLE BIT(3)
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#define MIISTATUS_LINK_IS_UP BIT(2)
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#define MIISTATUS_JABBER_DETECTED BIT(1)
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#define MIISTATUS_EXTENDED_CAPABILITIES_PRESENT BIT(0)
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#define MII4_MULTIPLE_PAGES BIT(15)
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#define MII4_REMOTE_FAULT BIT(13)
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#define MII4_ASYMETRIC_PAUSE BIT(11)
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#define MII4_PAUSE BIT(10)
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#define MII4_100BASE_T4 BIT(9)
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#define MII4_100BASE_T_FULL_DUPLEX BIT(8)
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#define MII4_100BASE_T_HALF_DUPLEX BIT(7)
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#define MII4_10BASE_T_FULL_DUPLEX BIT(6)
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#define MII4_10BASE_T_HALF_DUPLEX BIT(5)
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#define XNET_ETHERNET_LINK_ACTIVE 0x01 // Ethernet cable is connected and active
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#define XNET_ETHERNET_LINK_100MBPS 0x02 // Ethernet link is set to 100 Mbps
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#define XNET_ETHERNET_LINK_10MBPS 0x04 // Ethernet link is set to 10 Mbps
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#define XNET_ETHERNET_LINK_FULL_DUPLEX 0x08 // Ethernet link is in full duplex mode
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#define XNET_ETHERNET_LINK_HALF_DUPLEX 0x10 // Ethernet link is in half duplex mode
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typedef struct // base address 0xFEF00000
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{
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DWORD intr; // 000
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// Interrupt register
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// bit 7: reserved
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// bit 6 (MINT): MII interrupt
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// bit 5 (STINT): software timer interrupt
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// bit 4 (TCINT): transmit complete w/o error interrupt
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// bit 3 (TEINT): transmit complete with error interrupt
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// bit 2 (MISS): missed a frame
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// bit 1 (RCINT): receive complete w/o error interrupt
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// bit 0 (REINT): receive complete with error interrupt
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#define INTR_MINT BIT(6)
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#define INTR_STINT BIT(5)
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#define INTR_TCINT BIT(4)
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#define INTR_TEINT BIT(3)
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#define INTR_MISS BIT(2)
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#define INTR_RCINT BIT(1)
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#define INTR_REINT BIT(0)
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#define INTR_ALL (INTR_MINT | \
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INTR_TCINT | \
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INTR_TEINT | \
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INTR_MISS | \
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INTR_RCINT | \
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INTR_REINT)
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DWORD intr_mk; // 004
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// Master interrupt mask
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// bit 7: reserved
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// bit 6: MINT mask - 1 = enable and 0 = disable
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// bit 5: STINT mask
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// bit 4: TCINT mask
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// bit 3: TEINT mask
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// bit 2: MISS mask
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// bit 1: RCINT mask
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// bit 0: REINT mask
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DWORD swtr_cntl; // 008
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// Software timer control register
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// bit 1 (STEN): software timer enable
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// bit 0 (STREN): software timer reload enable
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DWORD swtr_itc; // 00c
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// Software timer register
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// bit 31-16: current software timer count
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// bit 15-0: software timer interval
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BYTE gap1[0x80 - 0x10];
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DWORD tx_cntl; // 080
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// Transmit control register
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// bit 31-22: reserved
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// bit 21 (UFLOM): underflow error mask
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// bit 20 (TCOLM): transmit late collision mask
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// bit 19 (LCARM): loss of carrier mask
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// bit 18 (DEFM): deferred mask
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// bit 17 (EXDEFM): excessive deferral mask
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// bit 16 (RTRYM): retry error mask
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// bit 15-12: reserved
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// bit 11-8: maximum number of retries on collisions
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// bit 7-6: MAC-PHY interface
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// bit 5 (TDEFEN): two-part deferral enable
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// bit 4 (FCSEN): FCS append enable
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// bit 3 (PADEN): pad enable
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// bit 2 (RTRYEN): retry enable
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// bit 1 (HDEN): half-duplex enable
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// bit 0: reserved
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#define TXCNTL_UFLOM BIT(21)
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#define TXCNTL_TCOLM BIT(20)
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#define TXCNTL_LCARM BIT(19)
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#define TXCNTL_DEFM BIT(18)
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#define TXCNTL_EXDEFM BIT(17)
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#define TXCNTL_RTRYM BIT(16)
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#define TXCNTL_RCSHIFT 8
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#define TXCNTL_PHYSHIFT 6
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#define TXCNTL_TDEFEN BIT(5)
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#define TXCNTL_FCSEN BIT(4)
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#define TXCNTL_PADEN BIT(3)
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#define TXCNTL_RTRYEN BIT(2)
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#define TXCNTL_HDEN BIT(1)
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#define PHY_TYPE_MII 0
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#define TXCNTL_DEFAULT (TXCNTL_UFLOM | \
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TXCNTL_TCOLM | \
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TXCNTL_LCARM | \
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TXCNTL_EXDEFM | \
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TXCNTL_RTRYM | \
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TXCNTL_TDEFEN | \
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TXCNTL_FCSEN | \
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TXCNTL_PADEN | \
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TXCNTL_RTRYEN | \
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TXCNTL_HDEN | \
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(PHY_TYPE_MII << TXCNTL_PHYSHIFT) | \
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(15 << TXCNTL_RCSHIFT))
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DWORD tx_en; // 084
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// Transmit enable register
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// bit 1: transmit enable
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#define TXEN_ENABLE BIT(0)
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DWORD tx_sta; // 088
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// Transmit status register
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// bit 31-22: reserved
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// bit 21 (UFLO): underflow error
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// bit 20 (TCOL): transmit late collision
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// bit 19 (LCAR): loss of carrier
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// bit 18 (DEF): deferred
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// bit 17 (EXDEF): excessive deferral
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// bit 16 (RTRY): retry error
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// bit 15-1: reserved
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// bit 0: transmit channel idle status
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#define TXSTA_UFLO BIT(21)
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#define TXSTA_TCOL BIT(20)
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#define TXSTA_LCAR BIT(19)
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#define TXSTA_DEF BIT(18)
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#define TXSTA_EXDEF BIT(17)
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#define TXSTA_RTRY BIT(16)
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#define TXSTA_BUSY BIT(0)
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DWORD rx_cntl_0; // 08c
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// Receive control
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// bit 31-23: reserved
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// bit 22 (FRAMM): frame alignment error mask
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// bit 21 (OFOLM): overflow error mask
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// bit 20 (CRCM): FCS error mask
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// bit 19 (LFERM): length error mask
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// bit 18 (MAXM): maximum length error mask
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// bit 17 (RLCOLM): receive late collision mask
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// bit 16 (RUNTM): runt receive mask
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// bit 15-9: reserved
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// bit 8 (RDEFEN): receive deferral enable
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// bit 7 (BRDIS): broadcast receive disable
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// bit 6 (RUNTEN): runt packet receive enable
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// bit 5 (AFEN): address filtering enable
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// bit 4 (LBEN): loopback enable
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// bit 3 (PAEN): pause enable
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// bit 2 (FCSREN): FCS relay enable
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// bit 1 (PADSEN): pad strip enable
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// bit 0: reserved
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#define RXCNTL_FRAMM BIT(22)
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#define RXCNTL_OFLOM BIT(21)
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#define RXCNTL_CRCM BIT(20)
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#define RXCNTL_LFERM BIT(19)
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#define RXCNTL_MAXM BIT(18)
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#define RXCNTL_RLCOLM BIT(17)
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#define RXCNTL_RUNTM BIT(16)
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#define RXCNTL_RDEFEN BIT(8)
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#define RXCNTL_BRDIS BIT(7)
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#define RXCNTL_RUNTEN BIT(6)
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#define RXCNTL_AFEN BIT(5)
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#define RXCNTL_LBEN BIT(4)
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#define RXCNTL_PAEN BIT(3)
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#define RXCNTL_FCSREN BIT(2)
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#define RXCNTL_PADSEN BIT(1)
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#define RXCNTL_DEFAULT (RXCNTL_FRAMM | \
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RXCNTL_OFLOM | \
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RXCNTL_CRCM | \
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RXCNTL_LFERM | \
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RXCNTL_MAXM | \
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RXCNTL_RLCOLM | \
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RXCNTL_RUNTM | \
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RXCNTL_AFEN)
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DWORD rx_cntl_1; // 090
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// Maximum receive frame size register
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DWORD rx_en; // 094
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// Receive enable register
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// bit 1: receive enable
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#define RXEN_ENABLE BIT(0)
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DWORD rx_sta; // 098
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// Receive status register
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// bit 31-23: reserved
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// bit 22 (FRAM): frame alignment error
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// bit 21 (OFOL): overflow error
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// bit 20 (CRC): FCS error
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// bit 19 (LFER): length error
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// bit 18 (MAX): maximum length error
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// bit 17 (RLCOL): receive late collision
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// bit 16 (RUNT): runt receive
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// bit 15-1: reserved
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// bit 0: receive channel idle status
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#define RXSTA_FRAM BIT(22)
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#define RXSTA_OFLO BIT(21)
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#define RXSTA_CRC BIT(20)
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#define RXSTA_LFER BIT(19)
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#define RXSTA_MAX BIT(18)
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#define RXSTA_RLCOL BIT(17)
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#define RXSTA_RUNT BIT(16)
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#define RXSTA_BUSY BIT(0)
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DWORD bkoff_cntl; // 09c
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// Backoff control register (for HomePNA)
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// bit 31-16: reserved
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// bit 15-8: slot time, 127 for IEEE 802.3
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// bit 7-0: random seed
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#define BKOFFCNTL_RSSHIFT 0
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#define BKOFFCNTL_STSHIFT 8
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#define BKOFFCNTL_DEFAULT ((8 << BKOFFCNTL_RSSHIFT) | \
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(127 << BKOFFCNTL_STSHIFT))
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DWORD tx_def; // 0a0
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// Transmit deferral timing register
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// bit 31-24: reserved
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// bit 23-16 (TIFG): number of clocks for inter-frame gap
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// when two-part deferral is disabled
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// bit 15-8 (TIFG2): number of clocks for the second part
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// inter-frame gap for two-part deferral
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// bit 7-0 (TIFG1): number of clocks for the first part
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// inter-frame gap for two-part deferral
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#define TXDEF_GSHIFT 16
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#define TXDEF_G2SHIFT 8
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#define TXDEF_G1SHIFT 0
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// Default values for IEEE 802.3
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#define TXDEF_DEFAULT ((15 << TXDEF_G1SHIFT) | \
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(7 << TXDEF_G2SHIFT) | \
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(22 << TXDEF_GSHIFT))
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DWORD rx_def; // 0a4
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// Receive deferral register
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// bit 7-0 (RIFG): number of clocks for inter-frame gap
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// when receive deferral is enabled
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#define RXDEF_DEFAULT 0x16
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DWORD uni0; // 0a8
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// Lower 32-bits of the unicast address
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DWORD uni1; // 0ac
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// Higher 16-bits of the unicast address
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DWORD mult0; // 0b0
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// Lower 32-bits of the multicast address
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DWORD mult1; // 0b4
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// Higher 16-bits of the multicast address
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DWORD mult_mk0; // 0b8
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// Lower 32-bits of the multicast address mask
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DWORD mult_mk1; // 0bc
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// Higher 16-bits of the multicast address mask
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BYTE gap2[0x100 - 0xc0];
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DWORD tx_dadr; // 100
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// Transmit descriptor ring physical address
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DWORD rx_dadr; // 104
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// Receive descriptor ring physical address
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DWORD dlen; // 108
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// Descriptor ring length register
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// bit 31-26: reserved
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// bit 25-16 (RDLEN): receive descriptor block length (-1)
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// bit 15-10: reserved
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// bit 9-0 (TDLEN): transmit descriptor block length (-1)
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DWORD tx_poll; // 10c
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// Transmit descriptor poll register
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// bit 31-17: reserved
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// bit 16 (TPEN): transmit poll enable
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// bit 15-0: transmit poll interval
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DWORD rx_poll; // 110
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// Receive descriptor poll register
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// bit 31-17: reserved
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// bit 16 (RPEN): receive poll enable
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// bit 15-0: receive poll interval
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// this is measured in 66MHz / 15ns clock cycles
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#define RXPOLL_EN BIT(16)
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#define RXPOLL_FREQ_100MPS 100
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#define RXPOLL_FREQ_10MPS 1000
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DWORD tx_pcnt; // 114
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// Current transmit poll count
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DWORD rx_pcnt; // 118
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// Current receive poll count
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DWORD tx_cur_dadr; // 11c
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// Current transmit descriptor physical address
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DWORD rx_cur_dadr; // 120
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// Current receive descriptor physical address
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DWORD tx_cur_prd0; // 124
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// Current transmit physical address
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DWORD tx_cur_prd1; // 128
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// bit 31-16: current status of actively transmited frame
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// bit 15-0: current number of bytes remaining
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DWORD rx_cur_prd0; // 12c
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// Current receive physical address
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DWORD rx_cur_prd1; // 130
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// bit 31-16: current status of actively received frame
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// bit 15-0: current number of bytes remaining
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DWORD tx_nxt_dadr; // 134
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// Next transmit descriptor physical address
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DWORD rx_nxt_dadr; // 138
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// Next receive descriptor physical address
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DWORD tx_fifo_wm; // 13c
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// Transmit FIFO watermarks
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// bit 31-24: reserved
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// bit 23-16: High watermark
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// bit 15-8: reserved
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// bit 7-0: Low watermark
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#define TXFIFOWM_HWSHIFT 16
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#define TXFIFOWM_LWSHIFT 0
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#define TXFIFOWM_DEFAULT ((0x10 << TXFIFOWM_LWSHIFT) | \
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(0x30 << TXFIFOWM_HWSHIFT))
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DWORD rx_fifo_wm; // 140
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// Receive FIFO watermarks
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// bit 31-24: reserved
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// bit 23-16: High watermark
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// bit 15-8: reserved
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// bit 7-0: Low watermark
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#define RXFIFOWM_HWSHIFT 16
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#define RXFIFOWM_LWSHIFT 0
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#define RXFIFOWM_DEFAULT ((0x10 << RXFIFOWM_LWSHIFT) | \
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(0x30 << RXFIFOWM_HWSHIFT))
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DWORD mode; // 144
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// Mode register
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// bit 4: buffer management reset
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// need to be set for >= 3.2us before it's cleared
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// bit 3: there is no active DMA transfer in progress
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// bit 2: disable DMA transfer
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// bit 1 (RXDM): receive demand
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// bit 0 (TXDM): transmit demand
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#define MODE_RESET_BUFFERS BIT(4)
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#define MODE_DMA_IDLE BIT(3)
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#define MODE_DISABLE_DMA BIT(2)
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#define MODE_RXDM BIT(1)
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#define MODE_TXDM BIT(0)
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BYTE gap3[0x180 - 0x148];
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DWORD mintr; // 180
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// MII interrupt register
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// bit 7-5: reserved
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// bit 4 (MPDI): MII PHY detect interrupt
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// bit 3 (MAPI): MII auto-polling interrupt
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// bit 2 (MCCI): MII command complete interrupt
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// bit 1 (MCCII): MII command complete internal interrupt
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// bit 0 (MREI): MII read error interrupt
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#define MINTR_MPDI BIT(4)
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#define MINTR_MAPI BIT(3)
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#define MINTR_MCCI BIT(2)
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#define MINTR_MCCII BIT(1)
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#define MINTR_MREI BIT(0)
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DWORD mintr_mk; // 184
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// MII interrupt mask register
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// bit 7-5: reserved
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// bit 4: MPDI mask - 1 to enable and 0 to disable
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// bit 3: MAPI mask
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// bit 2: MCCI mask
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// bit 1: MCCII mask
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// bit 0: MREI mask
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DWORD mii_cs; // 188
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// MII control and status register
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// bit 31-29: reserved
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// bit 28-24: PHY address
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// bit 23-21: reserved
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// bit 20 (APEN): auto-polling enable
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// bit 19-16 (APTI): auto-polling time interval
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// bit 15 (T4): 100BASE-T4
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// bit 14 (XFD): 100BASE-X full duplex
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// bit 13 (XHD): 100BASE-X half duplex
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// bit 12 (10FD): 10Mb/s full-duplex
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// bit 11 (10HD): 10Mb/s half-duplex
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// bit 10 (ET2FD): 100BASE-T2 full-duplex
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// bit 9 (T2HD): 100BASE-T2 half-duplex
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// bit 8 (EXST): extended status
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// bit 7: reserved
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// bit 6 (MFPS): MF preamble suppression
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// bit 5 (ANC): auto negotiation complete
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// bit 4 (RF): remote fault
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// bit 3 (ANA): auto-negotiation ability
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// bit 2 (LS): link status
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// bit 1 (JD): Jabber detect
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// bit 0 (EC): extended capability
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#define MIICS_PADRSHIFT 24
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#define MIICS_APEN BIT(20)
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#define MIICS_APSHIFT 16
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#define MIICS_T4 BIT(15)
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#define MIICS_XFD BIT(14)
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#define MIICS_XHD BIT(13)
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#define MIICS_10FD BIT(12)
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#define MIICS_10HD BIT(11)
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#define MIICS_ET2FD BIT(10)
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#define MIICS_T2HD BIT(9)
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#define MIICS_EXST BIT(8)
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#define MIICS_MFPS BIT(6)
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#define MIICS_ANC BIT(5)
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#define MIICS_RF BIT(4)
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#define MIICS_ANA BIT(3)
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#define MIICS_LS BIT(2)
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#define MIICS_JD BIT(1)
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#define MIICS_EC BIT(0)
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#define PHY_ADDR 1
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#define MIICS_DEFAULT ((PHY_ADDR << MIICS_PADRSHIFT) | \
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(4 << MIICS_APSHIFT) | \
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MIICS_APEN)
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DWORD mii_tm; // 18c
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// MII clock timer register
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// bit 15: MII timer status
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// bit 14-9: reserved
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// bit 8: MII timer enable
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// bit 7-0: MII timer interval
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#define MIITM_BUSY BIT(15)
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#define MIITM_EN BIT(8)
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#define MIITM_TISHIFT 0
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#define MIITM_INTERVAL 5
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#define MIITM_DEFAULT ((MIITM_INTERVAL << MIITM_TISHIFT) | MIITM_EN)
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#define PHYRW_TIMEOUT ((64*2*2*400*MIITM_INTERVAL/1000)*16)
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DWORD mdio_adr; // 190
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// MDIO address register
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// bit 15 (MDLK): MDIO lock
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// bit 14-11: reserved
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// bit 10 (MDRW): MDIO read/write
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// bit 9-5 (PHYADR): physical address of the PHY to be accessed
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// bit 4-0 (PHYREG): register address of the PHY to be accessed
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|
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#define MDIOADR_LOCK BIT(15)
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#define MDIOADR_WRITE BIT(10)
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#define MDIOADR_PHYSHIFT 5
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#define MDIOADR_REGSHIFT 0
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|
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DWORD mdio_data; // 194
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|
// MDIO data register
|
|
// bit 15-0 (PHYD): data for the last PHY read/write access
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|
|
|
BYTE gap4[0x200 - 0x198];
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|
|
|
DWORD pm_cntl; // 200
|
|
// Power management control register
|
|
|
|
struct {
|
|
DWORD crc;
|
|
DWORD mask0;
|
|
DWORD mask1;
|
|
DWORD mask2;
|
|
DWORD mask3;
|
|
} pmc_crc[5];
|
|
// Pattern match CRC registers
|
|
|
|
DWORD pmc_alias;
|
|
// PCI power management register 0 alias
|
|
|
|
DWORD pmcsr_alias;
|
|
// PCI power management register 1 alias
|
|
} volatile * PNICCSR;
|
|
|
|
#define PNicCsr() ((PNICCSR)XPCICFG_NIC_MEMORY_REGISTER_BASE_0)
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|
|
|
#endif // !_PHY_H_
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