767 lines
25 KiB
NASM
767 lines
25 KiB
NASM
title "Context Swap"
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;++
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;
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; Copyright (c) 1989 Microsoft Corporation
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;
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; Module Name:
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;
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; ctxswap.asm
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;
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; Abstract:
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;
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; This module implements the code necessary to field the dispatch
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; interrupt and to perform kernel initiated context switching.
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;
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; Author:
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;
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; Shie-Lin Tzong (shielint) 14-Jan-1990
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;
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; Environment:
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;
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; Kernel mode only.
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;
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; Revision History:
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;
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; 22-feb-90 bryanwi
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; write actual swap context procedure
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;
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;--
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.486p
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.xlist
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include ks386.inc
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include i386\kimacro.inc
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include callconv.inc
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.list
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EXTRNP HalClearSoftwareInterrupt,1,,FASTCALL
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EXTRNP HalRequestSoftwareInterrupt,1,,FASTCALL
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EXTRNP KiReadyThread,1,,FASTCALL
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EXTRNP KiWaitTest,2,,FASTCALL
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EXTRNP KfLowerIrql,1,,FASTCALL
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EXTRNP KfRaiseIrql,1,,FASTCALL
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EXTRNP _KeGetCurrentIrql,0
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EXTRNP _KeGetCurrentThread,0
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EXTRNP _KiDeliverApc,0
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EXTRNP _KiQuantumEnd,0
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EXTRNP _KeBugCheckEx,5
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EXTRNP _KeBugCheck,1
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extrn _KiTrap13:PROC
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extrn KiRetireDpcList:PROC
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extrn _KeTickCount:DWORD
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extrn _KiDispatcherReadyListHead:DWORD
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extrn _KiIdleSummary:DWORD
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extrn _KiReadySummary:DWORD
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extrn _KiPCR:DWORD
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extrn _KiIdleThread:DWORD
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if DBG
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extrn _KdDebuggerEnabled:BYTE
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EXTRNP _DbgBreakPoint,0
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extrn _DbgPrint:near
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endif
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ifdef DEVKIT
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extrn _KiDbgCtxSwapNotify:DWORD
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endif
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_TEXT SEGMENT PARA PUBLIC 'CODE'
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ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
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page ,132
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subttl "Unlock Dispatcher Database"
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;++
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;
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; VOID
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; KiUnlockDispatcherDatabase (
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; IN KIRQL OldIrql
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; )
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;
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; Routine Description:
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;
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; This routine is entered at IRQL DISPATCH_LEVEL with the dispatcher
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; database locked. Its function is to either unlock the dispatcher
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; database and return or initiate a context switch if another thread
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; has been selected for execution.
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;
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; Arguments:
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;
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; (TOS) Return address
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;
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; (ecx) OldIrql - Supplies the IRQL when the dispatcher database
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; lock was acquired.
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;
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; Return Value:
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;
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; None.
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;
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;--
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cPublicFastCall KiUnlockDispatcherDatabase, 1
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;
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; Check if a new thread is scheduled for execution.
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;
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cmp PCR[PcPrcbData+PbNextThread], 0 ; check if next thread
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jne short Kiu20 ; if ne, new thread scheduled
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;
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; Release dispatcher database lock, lower IRQL to its previous level,
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; and return.
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;
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Kiu00: ;
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;
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; N.B. This exit jumps directly to the lower IRQL routine which has a
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; compatible fastcall interface.
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;
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jmp @KfLowerIrql@4 ; lower IRQL to previous level
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;
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; A new thread has been selected to run on the current processor, but
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; the new IRQL is not below dispatch level. If the current processor is
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; not executing a DPC, then request a dispatch interrupt on the current
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; processor.
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;
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Kiu10: cmp dword ptr PCR[PcPrcbData.PbDpcRoutineActive],0 ; check if DPC routine active
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jne short Kiu00 ; if ne, DPC routine is active
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push ecx ; save new IRQL
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mov cl, DISPATCH_LEVEL ; request dispatch interrupt
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fstCall HalRequestSoftwareInterrupt ;
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pop ecx ; restore new IRQL
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;
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; N.B. This exit jumps directly to the lower IRQL routine which has a
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; compatible fastcall interface.
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;
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jmp @KfLowerIrql@4 ; lower IRQL to previous level
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;
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; Check if the previous IRQL is less than dispatch level.
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;
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Kiu20: cmp cl, DISPATCH_LEVEL ; check if IRQL below dispatch level
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jge short Kiu10 ; if ge, not below dispatch level
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;
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; There is a new thread scheduled for execution and the previous IRQL is
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; less than dispatch level. Context switch to the new thread immediately.
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;
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;
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; N.B. The following registers MUST be saved such that ebp is saved last.
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; This is done so the debugger can find the saved ebp for a thread
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; that is not currently in the running state.
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;
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.fpo (0, 0, 0, 4, 1, 0)
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sub esp, 4*4
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mov [esp+12], ebx ; save registers
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mov [esp+8], esi ;
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mov [esp+4], edi ;
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mov [esp+0], ebp ;
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lea ebx, _KiPCR ; get address of PCR
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mov esi, [ebx].PcPrcbData.PbNextThread ; get next thread address
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mov edi, [ebx].PcPrcbData.PbCurrentThread ; get current thread address
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mov dword ptr [ebx].PcPrcbData.PbNextThread, 0 ; clear next thread address
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mov [ebx].PcPrcbData.PbCurrentThread, esi ; set current thread address
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mov [edi].ThWaitIrql, cl ; save previous IRQL
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mov ecx, edi ; set address of current thread
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fstCall KiReadyThread ; reready thread for execution
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mov cl, [edi].ThWaitIrql ; set APC interrupt bypass disable
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call SwapContext ; swap context
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or al, al ; check if kernel APC pending
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mov cl, [esi].ThWaitIrql ; get original wait IRQL
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jnz short Kiu50 ; if nz, kernel APC pending
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Kiu30: mov ebp, [esp+0] ; restore registers
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mov edi, [esp+4] ;
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mov esi, [esp+8] ;
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mov ebx, [esp+12] ;
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add esp, 4*4
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;
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; N.B. This exit jumps directly to the lower IRQL routine which has a
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; compatible fastcall interface.
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;
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jmp @KfLowerIrql@4 ; lower IRQL to previous level
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Kiu50: mov cl, APC_LEVEL ; lower IRQL to APC level
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fstCall KfLowerIrql ;
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xor eax, eax ; set previous mode to kernel
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stdCall _KiDeliverApc ; deliver kernel mode APC
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xor ecx, ecx ; set original wait IRQL
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jmp short Kiu30
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fstENDP KiUnlockDispatcherDatabase
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page ,132
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subttl "Swap Thread"
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;++
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;
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; VOID
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; KiSwapThread (
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; VOID
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; )
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;
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; Routine Description:
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;
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; This routine is called to select the next thread to run on the
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; current processor and to perform a context switch to the thread.
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;
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; Arguments:
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;
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; None.
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;
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; Return Value:
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;
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; Wait completion status (eax).
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;
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;--
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cPublicFastCall KiSwapThread, 0
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.fpo (0, 0, 0, 4, 1, 0)
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;
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; N.B. The following registers MUST be saved such that ebp is saved last.
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; This is done so the debugger can find the saved ebp for a thread
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; that is not currently in the running state.
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;
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sub esp, 4*4
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mov [esp+12], ebx ; save registers
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mov [esp+8], esi ;
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mov [esp+4], edi ;
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mov [esp+0], ebp ;
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lea ebx, _KiPCR ; get address of PCR
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mov edx, [ebx].PcPrcbData.PbNextThread ; get next thread address
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or edx, edx ; check if next thread selected
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jnz Swt140 ; if nz, next thread selected
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;
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; Find the highest nibble in the ready summary that contains a set bit
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; and left justify so the nibble is in bits <31:28>
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;
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mov ecx, 16 ; set base bit number
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mov edi, _KiReadySummary ; get ready summary
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mov esi, edi ; copy ready summary
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shr esi, 16 ; isolate bits <31:16> of summary
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jnz short Swt10 ; if nz, bits <31:16> are nonzero
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xor ecx, ecx ; set base bit number
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mov esi, edi ; set bits <15:0> of summary
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Swt10: shr esi, 8 ; isolate bits <15:8> of low bits
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jz short Swt20 ; if z, bits <15:8> are zero
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add ecx, 8 ; add offset to nonzero byte
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Swt20: mov esi, edi ; isolate highest nonzero byte
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shr esi, cl ;
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add ecx, 3 ; adjust to high bit of nibble
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cmp esi, 10h ; check if high nibble nonzero
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jb short Swt30 ; if b, then high nibble is zero
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add ecx, 4 ; compute ready queue priority
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Swt30: mov esi, ecx ; left justify ready summary nibble
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not ecx ;
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shl edi, cl ;
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or edi, edi ;
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;
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; If the next bit is set in the ready summary, then scan the corresponding
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; dispatcher ready queue.
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;
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Swt40: js short Swt60 ; if s, queue contains an entry
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Swt50: sub esi, 1 ; decrement ready queue priority
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shl edi, 1 ; position next ready summary bit
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jnz short Swt40 ; if nz, more queues to scan
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;
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; All ready queues were scanned without finding a runnable thread so
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; default to the idle thread and set the appropriate bit in idle summary.
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;
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mov _KiIdleSummary, 1 ; set idle summary bit
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lea edx, _KiIdleThread ; set idle thread address
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jmp Swt140 ;
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;
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; If the thread can execute on the current processor, then remove it from
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; the dispatcher ready queue.
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;
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align 4
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swt60: lea ebp, [esi*8] + _KiDispatcherReadyListHead ; get ready queue address
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mov ecx, [ebp].LsFlink ; get address of first queue entry
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Swt70: mov edx, ecx ; compute address of thread object
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sub edx, ThWaitListEntry ;
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;
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; Remove the selected thread from the ready queue.
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;
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mov eax, [ecx].LsFlink ; get list entry forward link
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mov ebp, [ecx].LsBlink ; get list entry backward link
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mov [ebp].LsFlink, eax ; set forward link in previous entry
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mov [eax].LsBlink, ebp ; set backward link in next entry
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cmp eax, ebp ; check if list is empty
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jnz short Swt140 ; if nz, list is not empty
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mov ebp, 1 ; clear ready summary bit
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mov ecx, esi ;
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shl ebp, cl ;
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xor _KiReadySummary, ebp ;
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;
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; Swap context to the next thread.
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;
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Swt140: mov esi, edx ; set address of next thread
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mov edi, [ebx].PcPrcbData.PbCurrentThread ; set current thread address
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mov dword ptr [ebx].PcPrcbData.PbNextThread, 0 ; clear next thread address
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mov [ebx].PcPrcbData.PbCurrentThread, esi ; set current thread address
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mov cl, [edi].ThWaitIrql ; set APC interrupt bypass disable
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call SwapContext ; swap context
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or al, al ; check if kernel APC pending
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mov edi, [esi].ThWaitStatus ; save wait completion status
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mov cl, [esi].ThWaitIrql ; get wait IRQL
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jnz short Swt160 ; if nz, kernel APC pending
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Swt150: fstCall KfLowerIrql ; lower IRQL to previous value
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mov eax, edi ; set wait completion status
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mov ebp, [esp+0] ; restore registers
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mov edi, [esp+4] ;
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mov esi, [esp+8] ;
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mov ebx, [esp+12] ;
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add esp, 4*4 ;
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fstRET KiSwapThread ;
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Swt160: mov cl, APC_LEVEL ; lower IRQL to APC level
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fstCall KfLowerIrql ;
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xor eax, eax ; set previous mode to kernel
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stdCall _KiDeliverApc ; deliver kernel mode APC
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xor ecx, ecx ; set original wait IRQL
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jmp short Swt150
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fstENDP KiSwapThread
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page ,132
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subttl "Dispatch Interrupt"
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;++
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;
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; Routine Description:
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;
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; This routine is entered as the result of a software interrupt generated
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; at DISPATCH_LEVEL. Its function is to process the Deferred Procedure Call
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; (DPC) list, and then perform a context switch if a new thread has been
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; selected for execution on the processor.
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;
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; This routine is entered at IRQL DISPATCH_LEVEL with the dispatcher
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; database unlocked. When a return to the caller finally occurs, the
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; IRQL remains at DISPATCH_LEVEL, and the dispatcher database is still
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; unlocked.
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;
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; Arguments:
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;
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; None
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;
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; Return Value:
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;
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; None.
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;
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;--
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align 16
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cPublicProc _KiDispatchInterrupt ,0
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cPublicFpo 0, 0
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lea ebx, _KiPCR ; get address of PCR
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kdi00: lea eax, [ebx].PcPrcbData.PbDpcListHead ; get DPC listhead address
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;
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; Disable interrupts and check if there is any work in the DPC list
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; of the current processor.
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;
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kdi10: cli ; disable interrupts
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cmp eax, [eax].LsFlink ; check if DPC List is empty
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je short kdi40 ; if eq, list is empty
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push ebp ; save register
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;
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; Exceptions occuring in DPCs are unrelated to any exception handlers
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; in the interrupted thread. Terminate the exception list.
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;
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push [ebx].PcExceptionList
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mov [ebx].PcExceptionList, EXCEPTION_CHAIN_END
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;
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; Switch to the DPC stack for this processor.
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;
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mov edx, esp
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mov esp, [ebx].PcPrcbData.PbDpcStack
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push edx
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.fpo (0, 0, 0, 1, 1, 0)
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mov ebp, eax ; set address of DPC listhead
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call KiRetireDpcList ; process the current DPC list
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;
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; Switch back to the current thread stack, restore the exception list
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; and saved EBP.
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;
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pop esp
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pop [ebx].PcExceptionList
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pop ebp
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.fpo (0, 0, 0, 0, 0, 0)
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;
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; Check to determine if quantum end is requested.
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;
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; N.B. If a new thread is selected as a result of processing the quantum
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; end request, then the new thread is returned with the dispatcher
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; database locked. Otherwise, NULL is returned with the dispatcher
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; database unlocked.
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;
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kdi40: sti ; enable interrupts
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cmp dword ptr [ebx].PcPrcbData.PbQuantumEnd, 0 ; quantum end requested
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jne kdi90 ; if neq, quantum end request
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;
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; Check to determine if a new thread has been selected for execution on this
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; processor.
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;
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cmp dword ptr [ebx].PcPrcbData.PbNextThread, 0 ; check addr of next thread object
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je short kdi70 ; if eq, then no new thread
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;
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; Disable interrupts and attempt to acquire the dispatcher database lock.
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;
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mov eax, [ebx].PcPrcbData.PbNextThread ; get next thread address
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;
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; N.B. The following registers MUST be saved such that ebp is saved last.
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; This is done so the debugger can find the saved ebp for a thread
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; that is not currently in the running state.
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;
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.fpo (0, 0, 0, 3, 1, 0)
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kdi60: sub esp, 3*4
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mov [esp+8], esi ; save registers
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mov [esp+4], edi ;
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mov [esp+0], ebp ;
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mov esi, eax ; set next thread address
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mov edi, [ebx].PcPrcbData.PbCurrentThread ; get current thread address
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mov dword ptr [ebx].PcPrcbData.PbNextThread, 0 ; clear next thread address
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mov [ebx].PcPrcbData.PbCurrentThread, esi ; set current thread address
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mov ecx, edi ; set address of current thread
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fstCall KiReadyThread ; ready thread (ecx) for execution
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mov cl, 1 ; set APC interrupt bypass disable
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call SwapContext ; call context swap routine
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mov ebp, [esp+0] ; restore registers
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mov edi, [esp+4] ;
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mov esi, [esp+8] ;
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add esp, 3*4
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kdi70: stdRET _KiDispatchInterrupt ; return
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;
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; Process quantum end event.
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;
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; N.B. If the quantum end code returns a NULL value, then no next thread
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; has been selected for execution. Otherwise, a next thread has been
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; selected and the dispatcher databased is locked.
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;
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kdi90: mov dword ptr [ebx].PcPrcbData.PbQuantumEnd, 0 ; clear quantum end indicator
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stdCall _KiQuantumEnd ; process quantum end
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or eax, eax ; check if new thread selected
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jne short kdi60 ; if ne, new thread selected
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stdRET _KiDispatchInterrupt ; return
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stdENDP _KiDispatchInterrupt
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page ,132
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subttl "Swap Context to Next Thread"
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;++
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;
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; Routine Description:
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;
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; This routine is called to swap context from one thread to the next.
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; It swaps context, flushes the data, instruction, and translation
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; buffer caches, restores nonvolatile integer registers, and returns
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; to its caller.
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;
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; N.B. It is assumed that the caller (only callers are within this
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; module) saved the nonvolatile registers, ebx, esi, edi, and
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; ebp. This enables the caller to have more registers available.
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;
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; Arguments:
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;
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; cl - APC interrupt bypass disable (zero enable, nonzero disable).
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; edi - Address of previous thread.
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; esi - Address of next thread.
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; ebx - Address of PCR.
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;
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; Return value:
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;
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; al - Kernel APC pending.
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; ebx - Address of PCR.
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; esi - Address of current thread object.
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;
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;--
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align 16
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public SwapContext
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SwapContext proc
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;
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; NOTE: The ES: override on the move to ThState is part of the
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; lazy-segment load system. It assures that ES has a valid
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; selector in it, thus preventing us from propagating a bad
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; ES accross a context switch.
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;
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; Note that if segments, other than the standard flat segments,
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; with limits above 2 gig exist, neither this nor the rest of
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; lazy segment loads are reliable.
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;
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; Note that ThState must be set before the dispatcher lock is released
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; to prevent KiSetPriorityThread from seeing a stale value.
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;
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;
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; Save the APC disable flag and set new thread state to running.
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;
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or cl, cl ; set zf in flags
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mov byte ptr es:[esi]+ThState, Running ; set thread state to running
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pushfd
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cPublicFpo 0, 1
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;
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; Save the APC disable flag and the exception listhead.
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; (also, check for DPC running which is illegal right now).
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;
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mov ecx, [ebx]+PcExceptionList ; save exception list
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cmp [ebx]+PcPrcbData+PbDpcRoutineActive, 0
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push ecx
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cPublicFpo 0, 2
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jne sc91 ; bugcheck if DPC active.
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;
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; Notify the profiling function of the context switch.
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;
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ifdef DEVKIT
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cmp _KiDbgCtxSwapNotify, 0
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jne sc92
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sc03:
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endif ; DEVKIT
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;
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; On a uniprocessor system the NPX state is swapped in a lazy manner.
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; If a thread whose state is not in the coprocessor attempts to perform
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; a coprocessor operation, the current NPX state is swapped out (if needed),
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; and the new state is swapped in durning the fault. (KiTrap07)
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;
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; On a multiprocessor system we still fault in the NPX state on demand, but
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; we save the state when the thread switches out (assuming the NPX state
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; was loaded). This is because it could be difficult to obtain the thread's
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; NPX in the trap handler if it was loaded into a different processor's
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; coprocessor.
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;
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mov ebp, cr0 ; get current CR0
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mov edx, ebp
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;
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; Switch stacks:
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;
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; 1. Save old esp in old thread object.
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; 2. Copy stack base and stack limit into TSS AND PCR
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; 3. Load esp from new thread object
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;
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; Keep interrupts off so we don't confuse the trap handler into thinking
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; we've overrun the kernel stack.
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;
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cli ; disable interrupts
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mov [edi]+ThKernelStack, esp ; save old kernel stack pointer
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mov eax, [esi]+ThStackBase ; get new initial stack pointer
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mov ecx, [esi]+ThStackLimit ; get stack limit
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sub eax, NPX_FRAME_LENGTH ; space for NPX_FRAME & NPX CR0 flags
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mov [ebx]+PcStackLimit, ecx ; set new stack limit
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mov [ebx]+PcStackBase, eax ; set new stack base
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.errnz (NPX_STATE_NOT_LOADED - CR0_TS - CR0_MP)
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.errnz (NPX_STATE_LOADED - 0)
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; (eax) = Initial Stack
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; (ebx) = Prcb
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; (edi) = OldThread
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; (esi) = NewThread
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; (ebp) = Current CR0
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; (edx) = Current CR0
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xor ecx, ecx
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mov cl, [esi]+ThNpxState ; New NPX state is (or is not) loaded
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and edx, NOT (CR0_MP+CR0_EM+CR0_TS) ; clear thread settable NPX bits
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or ecx, edx ; or in new thread's cr0
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or ecx, [eax]+FpCr0NpxState ; merge new thread settable state
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cmp ebp, ecx ; check if old and new CR0 match
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jne sc_reload_cr0 ; if ne, no change in CR0
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align 4
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sc06: mov esp, [esi]+ThKernelStack ; set new stack pointer
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sti ; enable interrupts
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;
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; Update context switch counters.
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;
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inc dword ptr [esi]+ThContextSwitches ; thread count
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inc dword ptr [ebx]+PcPrcbData+PbContextSwitches ; processor count
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pop ecx ; restore exception list
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mov [ebx].PcExceptionList, ecx ;
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;
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; If the new thread has a kernel mode APC pending, then request an APC
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; interrupt.
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;
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cmp byte ptr [esi].ThApcState.AsKernelApcPending, 0 ; APC pending?
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jne short sc80 ; if ne, kernel APC pending
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popfd ; restore flags
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xor eax, eax ; clear kernel APC pending
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ret ; return
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;
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; The new thread has an APC interrupt pending. If APC interrupt bypass is
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; enable, then return kernel APC pending. Otherwise, request a software
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; interrupt at APC_LEVEL and return no kernel APC pending.
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;
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sc80: popfd ; restore flags
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jnz short sc90 ; if nz, APC interupt bypass disabled
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mov al, 1 ; set kernel APC pending
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ret ;
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sc90: mov cl, APC_LEVEL ; request software interrupt level
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fstCall HalRequestSoftwareInterrupt ;
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xor eax, eax ; clear kernel APC pending
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ret ;
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;
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; Cr0 has changed (ie, floating point processor present), load the new value.
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;
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sc_reload_cr0:
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if DBG
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test byte ptr [esi]+ThNpxState, NOT (CR0_TS+CR0_MP)
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jnz sc_error ;
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test dword ptr [eax]+FpCr0NpxState, NOT (CR0_PE+CR0_MP+CR0_EM+CR0_TS)
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jnz sc_error3 ;
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endif
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mov cr0,ecx ; set new CR0 NPX state
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jmp sc06
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;
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; Notify context swap callout routine. This code is out of line to
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; optimize the normal case (which is expected to be the case where
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; there is no callout routine).
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;
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ifdef DEVKIT
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sc92: mov edx, [esi].EtUniqueThread ; set new thread unique id
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mov ecx, [edi].EtUniqueThread ; set old thread unique id
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call [_KiDbgCtxSwapNotify] ; notify callout routine
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jmp sc03
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endif ; DEVKIT
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.fpo (2, 0, 0, 0, 0, 0)
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sc91: stdCall _KeBugCheck <ATTEMPTED_SWITCH_FROM_DPC>
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ret ; return
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if DBG
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sc_error5: int 3
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sc_error4: int 3
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sc_error3: int 3
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sc_error2: int 3
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sc_error: int 3
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endif
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SwapContext endp
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page , 132
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subttl "Flush EntireTranslation Buffer"
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;++
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;
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; VOID
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; KeFlushCurrentTb (
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; )
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;
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; Routine Description:
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;
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; This function flushes the entire translation buffer (TB) on the current
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; processor and also flushes the data cache if an entry in the translation
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; buffer has become invalid.
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;
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; Arguments:
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;
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; Return Value:
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;
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; None.
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;
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;--
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cPublicProc _KeFlushCurrentTb ,0
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mov eax, cr3 ; (eax) = directory table base
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mov cr3, eax ; flush TLB
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stdRET _KeFlushCurrentTb
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stdENDP _KeFlushCurrentTb
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cPublicProc _KeFlushCurrentTbAndInvalidateAllCaches ,0
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mov eax, cr3 ; (eax) = directory table base
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mov cr3, eax ; flush TLB
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cPublicProc _KeInvalidateAllCaches ,0
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wbinvd
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stdRET _KeFlushCurrentTbAndInvalidateAllCaches
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stdENDP _KeInvalidateAllCaches
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stdENDP _KeFlushCurrentTbAndInvalidateAllCaches
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_TEXT ends
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end
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