211 lines
7.2 KiB
C++
211 lines
7.2 KiB
C++
/***************************************************************************\
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|* *|
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|* Copyright (c) 1993-2000 NVIDIA, Corp. All rights reserved. *|
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|* *|
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|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
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|* international laws. NVIDIA, Corp. of Sunnyvale, California owns *|
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|* the copyright and as design patents pending on the design and *|
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|* interface of the NV chips. Users and possessors of this source *|
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|* code are hereby granted a nonexclusive, royalty-free copyright *|
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|* and design patent license to use this code in individual and *|
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|* commercial software. *|
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|* *|
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|* Any use of this source code must include, in the user documenta- *|
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|* tion and internal comments to the code, notices to the end user *|
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|* as follows: *|
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|* *|
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|* Copyright (c) 1993-2000 NVIDIA, Corp. NVIDIA design patents *|
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|* pending in the U.S. and foreign countries. *|
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|* *|
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|* NVIDIA, CORP. MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF *|
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|* THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT *|
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|* EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORP. DISCLAIMS *|
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|* ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, INCLUDING ALL *|
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|* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *|
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|* PARTICULAR PURPOSE. IN NO EVENT SHALL NVIDIA, CORP. BE LIABLE *|
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|* FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, *|
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|* OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR *|
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|* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER *|
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|* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR *|
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|* PERFORMANCE OF THIS SOURCE CODE. *|
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|* *|
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\***************************************************************************/
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/************************GP class for the HAL******************************\
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* *
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* Module: CHalGlobalProc.cpp *
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* All functions common to diff HALs are implemented here *
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* *
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*****************************************************************************
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* *
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* History: *
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* *
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\***************************************************************************/
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extern "C"
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{
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#include <nvarm.h>
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#include <AudioHw.h>
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#include <nv_papu.h>
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#include <aos.h>
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#include <nv32.h>
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};
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#include "CHalBase.h"
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#include "CObjBase.h"
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#include "CHalGlobalProc.h"
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CHalGlobalProc::CHalGlobalProc(CHalBase *pHal) : CObjBase(pHal)
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{
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m_CommandQ.Size = 4096;
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}
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RM_STATUS
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CHalGlobalProc::Allocate(VOID *pParam)
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{
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APU_AP_CREATE *pArg = (APU_AP_CREATE *)pParam;
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RM_STATUS rmStatus = RM_OK;
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do
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{
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rmStatus = GetCaps(pArg);
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if (rmStatus != RM_OK)
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break;
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rmStatus = AllocateMemory(pArg);
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if (rmStatus != RM_OK)
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break;
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InitializeHardware();
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} while (FALSE);
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return rmStatus;
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}
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RM_STATUS
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CHalGlobalProc::Free(VOID *pParam)
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{
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FreeMemory();
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return RM_OK;
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}
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RM_STATUS
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CHalGlobalProc::GetCaps(APU_AP_CREATE *pArg)
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{
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VOLU32 vTemp;
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// output from GP
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if (pArg->uSGEOutCount)
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{
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vTemp = pArg->uSGEOutCount - 1;
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RegWrite(NV_PAPU_FEMAXGPSGE, LOW16(vTemp));
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RegRead(NV_PAPU_FEMAXGPSGE, &vTemp);
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pArg->uSGEOutCount = vTemp + 1;
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}
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if (pArg->uGPScratch)
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{
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vTemp = pArg->uGPScratch - 1;
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RegWrite(NV_PAPU_GPSMAXSGE, LOW16(vTemp));
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RegRead(NV_PAPU_GPSMAXSGE, &vTemp);
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pArg->uGPScratch = vTemp + 1;
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}
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return RM_OK;
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}
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RM_STATUS
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CHalGlobalProc::AllocateMemory(APU_AP_CREATE *pArg)
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{
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m_SgeOut.Size = pArg->uSGEOutCount * NV_PSGE_SIZE;
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m_Scratch.Size = pArg->uGPScratch * NV_PSGE_SIZE;
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RM_STATUS rmStatus = aosAllocateMem(m_SgeOut.Size,
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ALIGN_16K,
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&m_SgeOut.pLinAddr,
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&m_SgeOut.pPhysAddr);
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if (rmStatus == RM_OK)
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{
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// allocate memory for the command Q
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rmStatus = aosAllocateMem(m_CommandQ.Size,
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ALIGN_16K,
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&m_CommandQ.pLinAddr,
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&m_CommandQ.pPhysAddr);
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}
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// allocate memory for 1PRD to point to the 4K command Q
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if (rmStatus == RM_OK)
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{
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// allocate memory scratch area
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rmStatus = aosAllocateMem(m_Scratch.Size,
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ALIGN_16K,
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&m_Scratch.pLinAddr,
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&m_Scratch.pPhysAddr);
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}
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return rmStatus;
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}
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VOID
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CHalGlobalProc::FreeMemory()
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{
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aosFreeMem(m_SgeOut.pLinAddr);
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aosFreeMem(m_CommandQ.pLinAddr);
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aosFreeMem(m_Scratch.pLinAddr);
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}
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VOID
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CHalGlobalProc::InitializeHardware()
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{
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// clear any pending interrupts! - todo cleanup
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RegWrite(NV_PAPU_GPISTS, (U032)0xFFFFFFFF);
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/*
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// set up the Q ptrs .. JLT
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RegWrite(NV_PAPU_GPOFBASE0, (U032)0);
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RegWrite(NV_PAPU_GPOFEND0, m_SgeOut.Size);
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RegWrite(NV_PAPU_GPOFCUR0, (U032)0);
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RegWrite(NV_PAPU_GPOFBASE1, (U032)0);
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RegWrite(NV_PAPU_GPOFEND1, m_SgeOut.Size);
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RegWrite(NV_PAPU_GPOFCUR1, (U032)0);
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RegWrite(NV_PAPU_GPOFBASE2, (U032)0);
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RegWrite(NV_PAPU_GPOFEND2, m_SgeOut.Size);
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RegWrite(NV_PAPU_GPOFCUR2, (U032)0);
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RegWrite(NV_PAPU_GPOFBASE3, (U032)0);
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RegWrite(NV_PAPU_GPOFEND3, m_SgeOut.Size);
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RegWrite(NV_PAPU_GPOFCUR3, (U032)0);
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*/
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// output buffer PRDs
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RegWrite(NV_PAPU_GPFADDR, (U032)m_SgeOut.pPhysAddr);
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// scratch area for the GP
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RegWrite(NV_PAPU_GPSADDR, (U032)m_Scratch.pPhysAddr);
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// PRDs for the FIFO
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RegWrite(NV_PAPU_GPCADDR, (U032)m_CommandQ.pPhysAddr);
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}
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VOID
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CHalGlobalProc::WriteCommand(DSP_CONTROL *pDspWord, WORD4 *pW4, WORD5 *pW5, WORD6 *pW6)
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{
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RegWrite(NV_PAPU_GPXMEM(0), pDspWord->w0.uValue);
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RegWrite(NV_PAPU_GPXMEM(1), pDspWord->w1.uValue);
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RegWrite(NV_PAPU_GPXMEM(2), pDspWord->w2.uValue);
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RegWrite(NV_PAPU_GPXMEM(3), pDspWord->w3.uValue);
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if (pW4)
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RegWrite(NV_PAPU_GPXMEM(4), pW4->uValue);
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if (pW5)
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RegWrite(NV_PAPU_GPXMEM(5), pW5->uValue);
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if (pW6)
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RegWrite(NV_PAPU_GPXMEM(6), pW6->uValue);
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}
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