2016-05-24 08:35:23 +02:00
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// Copyright (c) 2011-present, Facebook, Inc. All rights reserved.
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2017-07-16 01:03:42 +02:00
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// This source code is licensed under both the GPLv2 (found in the
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// COPYING file in the root directory) and Apache 2.0 License
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// (found in the LICENSE.Apache file in the root directory).
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2016-05-24 08:35:23 +02:00
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#include "rocksdb/utilities/sim_cache.h"
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#include <atomic>
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2019-09-16 19:31:27 +02:00
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#include "file/writable_file_writer.h"
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2017-04-06 04:02:00 +02:00
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#include "monitoring/statistics.h"
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2016-07-21 00:28:04 +02:00
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#include "port/port.h"
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2017-07-28 21:18:09 +02:00
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#include "rocksdb/env.h"
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#include "util/mutexlock.h"
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#include "util/string_util.h"
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2016-05-24 08:35:23 +02:00
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namespace rocksdb {
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namespace {
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2017-07-28 21:18:09 +02:00
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class CacheActivityLogger {
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public:
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CacheActivityLogger()
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: activity_logging_enabled_(false), max_logging_size_(0) {}
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~CacheActivityLogger() {
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MutexLock l(&mutex_);
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StopLoggingInternal();
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}
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Status StartLogging(const std::string& activity_log_file, Env* env,
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uint64_t max_logging_size = 0) {
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assert(activity_log_file != "");
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assert(env != nullptr);
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Status status;
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EnvOptions env_opts;
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std::unique_ptr<WritableFile> log_file;
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MutexLock l(&mutex_);
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// Stop existing logging if any
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StopLoggingInternal();
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// Open log file
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status = env->NewWritableFile(activity_log_file, &log_file, env_opts);
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if (!status.ok()) {
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return status;
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}
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2018-08-23 19:04:10 +02:00
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file_writer_.reset(new WritableFileWriter(std::move(log_file),
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activity_log_file, env_opts));
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2017-07-28 21:18:09 +02:00
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max_logging_size_ = max_logging_size;
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activity_logging_enabled_.store(true);
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return status;
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}
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void StopLogging() {
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MutexLock l(&mutex_);
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StopLoggingInternal();
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}
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void ReportLookup(const Slice& key) {
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if (activity_logging_enabled_.load() == false) {
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return;
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}
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std::string log_line = "LOOKUP - " + key.ToString(true) + "\n";
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// line format: "LOOKUP - <KEY>"
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MutexLock l(&mutex_);
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Status s = file_writer_->Append(log_line);
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if (!s.ok() && bg_status_.ok()) {
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bg_status_ = s;
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}
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if (MaxLoggingSizeReached() || !bg_status_.ok()) {
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// Stop logging if we have reached the max file size or
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// encountered an error
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StopLoggingInternal();
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}
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}
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void ReportAdd(const Slice& key, size_t size) {
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if (activity_logging_enabled_.load() == false) {
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return;
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}
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std::string log_line = "ADD - ";
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log_line += key.ToString(true);
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log_line += " - ";
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AppendNumberTo(&log_line, size);
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2018-01-29 21:43:56 +01:00
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// @lint-ignore TXT2 T25377293 Grandfathered in
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2017-07-28 21:18:09 +02:00
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log_line += "\n";
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// line format: "ADD - <KEY> - <KEY-SIZE>"
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MutexLock l(&mutex_);
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Status s = file_writer_->Append(log_line);
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if (!s.ok() && bg_status_.ok()) {
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bg_status_ = s;
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}
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if (MaxLoggingSizeReached() || !bg_status_.ok()) {
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// Stop logging if we have reached the max file size or
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// encountered an error
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StopLoggingInternal();
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}
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}
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Status& bg_status() {
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MutexLock l(&mutex_);
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return bg_status_;
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}
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private:
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bool MaxLoggingSizeReached() {
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mutex_.AssertHeld();
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return (max_logging_size_ > 0 &&
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file_writer_->GetFileSize() >= max_logging_size_);
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}
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void StopLoggingInternal() {
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mutex_.AssertHeld();
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if (!activity_logging_enabled_) {
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return;
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}
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activity_logging_enabled_.store(false);
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Status s = file_writer_->Close();
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if (!s.ok() && bg_status_.ok()) {
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bg_status_ = s;
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}
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}
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// Mutex to sync writes to file_writer, and all following
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// class data members
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port::Mutex mutex_;
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// Indicates if logging is currently enabled
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// atomic to allow reads without mutex
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std::atomic<bool> activity_logging_enabled_;
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// When reached, we will stop logging and close the file
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// Value of 0 means unlimited
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uint64_t max_logging_size_;
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std::unique_ptr<WritableFileWriter> file_writer_;
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Status bg_status_;
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};
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2016-05-24 08:35:23 +02:00
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// SimCacheImpl definition
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class SimCacheImpl : public SimCache {
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public:
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// capacity for real cache (ShardedLRUCache)
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// test_capacity for key only cache
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Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
2019-06-18 01:33:40 +02:00
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SimCacheImpl(std::shared_ptr<Cache> sim_cache, std::shared_ptr<Cache> cache)
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2016-05-24 08:35:23 +02:00
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: cache_(cache),
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Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
2019-06-18 01:33:40 +02:00
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key_only_cache_(sim_cache),
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2016-08-11 02:42:24 +02:00
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miss_times_(0),
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2017-11-28 22:15:20 +01:00
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hit_times_(0),
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stats_(nullptr) {}
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2016-05-24 08:35:23 +02:00
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2019-02-14 22:52:47 +01:00
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~SimCacheImpl() override {}
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void SetCapacity(size_t capacity) override { cache_->SetCapacity(capacity); }
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2016-05-24 08:35:23 +02:00
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2019-02-14 22:52:47 +01:00
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void SetStrictCapacityLimit(bool strict_capacity_limit) override {
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2016-05-24 08:35:23 +02:00
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cache_->SetStrictCapacityLimit(strict_capacity_limit);
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}
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2019-02-14 22:52:47 +01:00
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Status Insert(const Slice& key, void* value, size_t charge,
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void (*deleter)(const Slice& key, void* value), Handle** handle,
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Priority priority) override {
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2016-05-24 08:35:23 +02:00
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// The handle and value passed in are for real cache, so we pass nullptr
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// to key_only_cache_ for both instead. Also, the deleter function pointer
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// will be called by user to perform some external operation which should
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// be applied only once. Thus key_only_cache accepts an empty function.
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// *Lambda function without capture can be assgined to a function pointer
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Handle* h = key_only_cache_->Lookup(key);
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if (h == nullptr) {
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key_only_cache_->Insert(key, nullptr, charge,
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2018-04-13 02:55:14 +02:00
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[](const Slice& /*k*/, void* /*v*/) {}, nullptr,
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2016-08-20 01:43:31 +02:00
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priority);
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2016-05-24 08:35:23 +02:00
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} else {
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key_only_cache_->Release(h);
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}
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2017-07-28 21:18:09 +02:00
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cache_activity_logger_.ReportAdd(key, charge);
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Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
2019-06-18 01:33:40 +02:00
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if (!cache_) {
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return Status::OK();
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}
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2016-08-20 01:43:31 +02:00
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return cache_->Insert(key, value, charge, deleter, handle, priority);
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2016-05-24 08:35:23 +02:00
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}
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2019-02-14 22:52:47 +01:00
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Handle* Lookup(const Slice& key, Statistics* stats) override {
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2016-05-24 08:35:23 +02:00
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Handle* h = key_only_cache_->Lookup(key);
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if (h != nullptr) {
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key_only_cache_->Release(h);
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inc_hit_counter();
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2016-09-01 22:50:39 +02:00
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RecordTick(stats, SIM_BLOCK_CACHE_HIT);
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2016-08-11 02:42:24 +02:00
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} else {
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inc_miss_counter();
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2016-09-01 22:50:39 +02:00
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RecordTick(stats, SIM_BLOCK_CACHE_MISS);
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2016-05-24 08:35:23 +02:00
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}
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2017-07-28 21:18:09 +02:00
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cache_activity_logger_.ReportLookup(key);
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Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
2019-06-18 01:33:40 +02:00
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if (!cache_) {
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return nullptr;
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}
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2016-09-01 22:50:39 +02:00
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return cache_->Lookup(key, stats);
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2016-05-24 08:35:23 +02:00
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}
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2019-02-14 22:52:47 +01:00
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bool Ref(Handle* handle) override { return cache_->Ref(handle); }
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2017-01-11 01:48:23 +01:00
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2019-02-14 22:52:47 +01:00
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bool Release(Handle* handle, bool force_erase = false) override {
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2017-04-24 20:21:47 +02:00
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return cache_->Release(handle, force_erase);
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}
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2016-05-24 08:35:23 +02:00
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2019-02-14 22:52:47 +01:00
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void Erase(const Slice& key) override {
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2016-05-24 08:35:23 +02:00
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cache_->Erase(key);
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key_only_cache_->Erase(key);
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}
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2019-02-14 22:52:47 +01:00
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void* Value(Handle* handle) override { return cache_->Value(handle); }
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2016-05-24 08:35:23 +02:00
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2019-02-14 22:52:47 +01:00
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uint64_t NewId() override { return cache_->NewId(); }
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2016-05-24 08:35:23 +02:00
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2019-02-14 22:52:47 +01:00
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size_t GetCapacity() const override { return cache_->GetCapacity(); }
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2016-05-24 08:35:23 +02:00
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2019-02-14 22:52:47 +01:00
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bool HasStrictCapacityLimit() const override {
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2016-05-24 08:35:23 +02:00
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return cache_->HasStrictCapacityLimit();
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}
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2019-02-14 22:52:47 +01:00
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size_t GetUsage() const override { return cache_->GetUsage(); }
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2016-05-24 08:35:23 +02:00
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2019-02-14 22:52:47 +01:00
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size_t GetUsage(Handle* handle) const override {
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2016-07-15 19:41:36 +02:00
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return cache_->GetUsage(handle);
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2016-05-24 08:35:23 +02:00
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}
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2019-06-19 02:32:44 +02:00
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size_t GetCharge(Handle* handle) const override { return cache_->GetCharge(handle); }
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2019-02-14 22:52:47 +01:00
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size_t GetPinnedUsage() const override { return cache_->GetPinnedUsage(); }
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2016-05-24 08:35:23 +02:00
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2019-02-14 22:52:47 +01:00
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void DisownData() override {
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2016-05-24 08:35:23 +02:00
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cache_->DisownData();
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key_only_cache_->DisownData();
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}
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2019-02-14 22:52:47 +01:00
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void ApplyToAllCacheEntries(void (*callback)(void*, size_t),
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bool thread_safe) override {
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2016-05-24 08:35:23 +02:00
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// only apply to _cache since key_only_cache doesn't hold value
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cache_->ApplyToAllCacheEntries(callback, thread_safe);
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}
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2019-02-14 22:52:47 +01:00
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void EraseUnRefEntries() override {
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2016-05-24 08:35:23 +02:00
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cache_->EraseUnRefEntries();
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key_only_cache_->EraseUnRefEntries();
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}
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2019-02-14 22:52:47 +01:00
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size_t GetSimCapacity() const override {
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2016-05-24 08:35:23 +02:00
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return key_only_cache_->GetCapacity();
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}
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2019-02-14 22:52:47 +01:00
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size_t GetSimUsage() const override { return key_only_cache_->GetUsage(); }
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void SetSimCapacity(size_t capacity) override {
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2016-05-24 08:35:23 +02:00
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key_only_cache_->SetCapacity(capacity);
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}
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2019-02-14 22:52:47 +01:00
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uint64_t get_miss_counter() const override {
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2016-08-11 02:42:24 +02:00
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return miss_times_.load(std::memory_order_relaxed);
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2016-07-15 19:41:36 +02:00
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}
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2019-02-14 22:52:47 +01:00
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uint64_t get_hit_counter() const override {
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2016-07-15 19:41:36 +02:00
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return hit_times_.load(std::memory_order_relaxed);
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}
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2019-02-14 22:52:47 +01:00
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void reset_counter() override {
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2016-08-11 02:42:24 +02:00
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miss_times_.store(0, std::memory_order_relaxed);
|
2016-07-15 19:41:36 +02:00
|
|
|
hit_times_.store(0, std::memory_order_relaxed);
|
2016-08-11 02:42:24 +02:00
|
|
|
SetTickerCount(stats_, SIM_BLOCK_CACHE_HIT, 0);
|
|
|
|
SetTickerCount(stats_, SIM_BLOCK_CACHE_MISS, 0);
|
2016-05-24 08:35:23 +02:00
|
|
|
}
|
|
|
|
|
2019-02-14 22:52:47 +01:00
|
|
|
std::string ToString() const override {
|
2016-05-24 08:35:23 +02:00
|
|
|
std::string res;
|
2016-08-11 02:42:24 +02:00
|
|
|
res.append("SimCache MISSes: " + std::to_string(get_miss_counter()) + "\n");
|
2016-05-24 08:35:23 +02:00
|
|
|
res.append("SimCache HITs: " + std::to_string(get_hit_counter()) + "\n");
|
2016-12-15 04:20:42 +01:00
|
|
|
char buff[350];
|
2016-08-11 02:42:24 +02:00
|
|
|
auto lookups = get_miss_counter() + get_hit_counter();
|
2016-05-24 08:35:23 +02:00
|
|
|
snprintf(buff, sizeof(buff), "SimCache HITRATE: %.2f%%\n",
|
2016-08-11 02:42:24 +02:00
|
|
|
(lookups == 0 ? 0 : get_hit_counter() * 100.0f / lookups));
|
2016-05-24 08:35:23 +02:00
|
|
|
res.append(buff);
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
2019-02-14 22:52:47 +01:00
|
|
|
std::string GetPrintableOptions() const override {
|
2016-12-22 23:44:01 +01:00
|
|
|
std::string ret;
|
|
|
|
ret.reserve(20000);
|
|
|
|
ret.append(" cache_options:\n");
|
|
|
|
ret.append(cache_->GetPrintableOptions());
|
|
|
|
ret.append(" sim_cache_options:\n");
|
|
|
|
ret.append(key_only_cache_->GetPrintableOptions());
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2019-02-14 22:52:47 +01:00
|
|
|
Status StartActivityLogging(const std::string& activity_log_file, Env* env,
|
|
|
|
uint64_t max_logging_size = 0) override {
|
2017-07-28 21:18:09 +02:00
|
|
|
return cache_activity_logger_.StartLogging(activity_log_file, env,
|
|
|
|
max_logging_size);
|
|
|
|
}
|
|
|
|
|
2019-02-14 22:52:47 +01:00
|
|
|
void StopActivityLogging() override { cache_activity_logger_.StopLogging(); }
|
2017-07-28 21:18:09 +02:00
|
|
|
|
2019-02-14 22:52:47 +01:00
|
|
|
Status GetActivityLoggingStatus() override {
|
2017-07-28 21:18:09 +02:00
|
|
|
return cache_activity_logger_.bg_status();
|
|
|
|
}
|
|
|
|
|
2016-05-24 08:35:23 +02:00
|
|
|
private:
|
|
|
|
std::shared_ptr<Cache> cache_;
|
|
|
|
std::shared_ptr<Cache> key_only_cache_;
|
2016-08-11 02:42:24 +02:00
|
|
|
std::atomic<uint64_t> miss_times_;
|
2016-05-24 08:35:23 +02:00
|
|
|
std::atomic<uint64_t> hit_times_;
|
2016-08-11 02:42:24 +02:00
|
|
|
Statistics* stats_;
|
2017-07-28 21:18:09 +02:00
|
|
|
CacheActivityLogger cache_activity_logger_;
|
|
|
|
|
2016-08-11 02:42:24 +02:00
|
|
|
void inc_miss_counter() {
|
|
|
|
miss_times_.fetch_add(1, std::memory_order_relaxed);
|
2016-07-15 19:41:36 +02:00
|
|
|
}
|
|
|
|
void inc_hit_counter() { hit_times_.fetch_add(1, std::memory_order_relaxed); }
|
2016-05-24 08:35:23 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
} // end anonymous namespace
|
|
|
|
|
|
|
|
// For instrumentation purpose, use NewSimCache instead
|
|
|
|
std::shared_ptr<SimCache> NewSimCache(std::shared_ptr<Cache> cache,
|
2016-09-01 22:50:39 +02:00
|
|
|
size_t sim_capacity, int num_shard_bits) {
|
2019-09-17 00:14:51 +02:00
|
|
|
LRUCacheOptions co;
|
|
|
|
co.capacity = sim_capacity;
|
|
|
|
co.num_shard_bits = num_shard_bits;
|
|
|
|
co.metadata_charge_policy = kDontChargeCacheMetadata;
|
|
|
|
return NewSimCache(NewLRUCache(co), cache, num_shard_bits);
|
Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
2019-06-18 01:33:40 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
std::shared_ptr<SimCache> NewSimCache(std::shared_ptr<Cache> sim_cache,
|
|
|
|
std::shared_ptr<Cache> cache,
|
|
|
|
int num_shard_bits) {
|
2016-05-24 08:35:23 +02:00
|
|
|
if (num_shard_bits >= 20) {
|
|
|
|
return nullptr; // the cache cannot be sharded into too many fine pieces
|
|
|
|
}
|
Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
2019-06-18 01:33:40 +02:00
|
|
|
return std::make_shared<SimCacheImpl>(sim_cache, cache);
|
2016-05-24 08:35:23 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
} // end namespace rocksdb
|