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fix: build on risc-v (#9215)

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Summary:
Patch is modified from ~~https://reviews.llvm.org/file/data/du5ol5zctyqw53ma7dwz/PHID-FILE-knherxziu4tl4erti5ab/file~~

Tested on Arch Linux riscv64gc (qemu)

UPDATE: Seems like the above link is broken, so I tried to search for a link pointing to the original merge request. It turned out to me that the LLVM guys are cherry-picking from `google/benchmark`, and the upstream should be this:

808571a52f/src/cycleclock.h (L190)

Pull Request resolved: https://github.com/facebook/rocksdb/pull/9215

Reviewed By: siying, jay-zhuang

Differential Revision: D34170586

Pulled By: riversand963

fbshipit-source-id: 41b16b9f7f3bb0f3e7b26bb078eb575499c0f0f4
This commit is contained in:
XieJiSS 2022-05-17 17:33:01 -07:00 committed by Facebook GitHub Bot
parent 3573558ec5
commit 8b1df101da
1 changed files with 17 additions and 0 deletions
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17
utilities/transactions/lock/range/range_tree/lib/portability/toku_time.h
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@ -137,6 +137,23 @@ static inline tokutime_t toku_time_now(void) {
uint64_t result; uint64_t result;
asm volatile("stckf %0" : "=Q"(result) : : "cc"); asm volatile("stckf %0" : "=Q"(result) : : "cc");
return result; return result;
#elif defined(__riscv) && __riscv_xlen == 32
uint32_t cycles_lo, cycles_hi0, cycles_hi1;
// Implemented in assembly because Clang insisted on branching.
asm volatile(
"rdcycleh %0\n"
"rdcycle %1\n"
"rdcycleh %2\n"
"sub %0, %0, %2\n"
"seqz %0, %0\n"
"sub %0, zero, %0\n"
"and %1, %1, %0\n"
: "=r"(cycles_hi0), "=r"(cycles_lo), "=r"(cycles_hi1));
return (static_cast<uint64_t>(cycles_hi1) << 32) | cycles_lo;
#elif defined(__riscv) && __riscv_xlen == 64
uint64_t cycles;
asm volatile("rdcycle %0" : "=r"(cycles));
return cycles;
#else #else
#error No timer implementation for this platform #error No timer implementation for this platform
#endif #endif