From ccf5f08f882038e8b481fafa0a0c0b1a04f6a390 Mon Sep 17 00:00:00 2001 From: Daniel Black Date: Fri, 14 Jul 2017 15:12:47 -0700 Subject: [PATCH] Set CACHE_LINE_SIZE for s390, PPC, ARM64 Summary: Closes https://github.com/facebook/rocksdb/pull/2579 Differential Revision: D5427667 Pulled By: maysamyabandeh fbshipit-source-id: cd0b076aa0cd38d3554516f01723c548713ece61 --- port/port_posix.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/port/port_posix.h b/port/port_posix.h index d7cd2659e..e02224828 100644 --- a/port/port_posix.h +++ b/port/port_posix.h @@ -186,7 +186,13 @@ typedef pthread_once_t OnceType; extern void InitOnce(OnceType* once, void (*initializer)()); #ifndef CACHE_LINE_SIZE -#define CACHE_LINE_SIZE 64U + #if defined(__s390__) + #define CACHE_LINE_SIZE 256U + #elif defined(__powerpc__) || defined(__aarch64__) + #define CACHE_LINE_SIZE 128U + #else + #define CACHE_LINE_SIZE 64U + #endif #endif #define PREFETCH(addr, rw, locality) __builtin_prefetch(addr, rw, locality)