Aaron Gao
2914de64e8
add sim_cache stats to Statistics
...
Summary:
add SIM_BLOCK_CACHE_HIT and SIM_BLOCK_CACHE_MISS tickers.
maybe can be combined with Histograms like DB_GET to evaluate the current setting of the size of block cache.
Test Plan: make all check
Reviewers: sdong, andrewkr, IslamAbdelRahman, yiwu
Reviewed By: yiwu
Subscribers: andrewkr, dhruba, leveldb
Differential Revision: https://reviews.facebook.net/D61803
2016-08-10 17:42:24 -07:00
John Alexander
9ab38c45ad
Remove %z Format Specifier and Fix Windows Build of sim_cache.cc ( #1224 )
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* Replace %zu format specifier with Windows-compatible macro 'ROCKSDB_PRIszt'
* Added "port/port.h" include to sim_cache.cc for call to snprintf().
* Applied cleaner fix to windows build, reverting part of 7bedd94
2016-07-20 15:28:04 -07:00
krad
7bedd94406
Build break fix
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Summary:
(1) Integer size correction (mac build break)
(2) snprint usage in Windows (windows build break)
Test Plan: Build in windows and mac
Reviewers: sdong
Subscribers: andrewkr, dhruba
Differential Revision: https://reviews.facebook.net/D60927
2016-07-20 10:56:43 -07:00
Yi Wu
4b95253587
Refactor cache.cc
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Summary: Refactor cache.cc so that I can plugin clock cache (D55581). Mainly move `ShardedCache` to separate file, move `LRUHandle` back to cache.cc and rename it lru_cache.cc.
Test Plan:
make check -j64
Reviewers: lightmark, sdong
Reviewed By: sdong
Subscribers: andrewkr, dhruba, leveldb
Differential Revision: https://reviews.facebook.net/D59655
2016-07-15 10:41:36 -07:00
Aaron Gao
630b732cb3
fix flaky sim_cache_test
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Summary: fix flaky test
Test Plan: `make all check`
Reviewers: sdong, andrewkr
Reviewed By: andrewkr
Subscribers: andrewkr, dhruba, leveldb
Differential Revision: https://reviews.facebook.net/D59157
2016-06-02 18:39:25 -07:00
Aaron Gao
5d660258e7
add simulator Cache as class SimCache/SimLRUCache(with test)
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Summary: add class SimCache(base class with instrumentation api) and SimLRUCache(derived class with detailed implementation) which is used as an instrumented block cache that can predict hit rate for different cache size
Test Plan:
Add a test case in `db_block_cache_test.cc` called `SimCacheTest` to test basic logic of SimCache.
Also add option `-simcache_size` in db_bench. if set with a value other than -1, then the benchmark will use this value as the size of the simulator cache and finally output the simulation result.
```
[gzh@dev9927.prn1 ~/local/rocksdb] ./db_bench -benchmarks "fillseq,readrandom" -cache_size 1000000 -simcache_size 1000000
RocksDB: version 4.8
Date: Tue May 17 16:56:16 2016
CPU: 32 * Intel(R) Xeon(R) CPU E5-2660 0 @ 2.20GHz
CPUCache: 20480 KB
Keys: 16 bytes each
Values: 100 bytes each (50 bytes after compression)
Entries: 1000000
Prefix: 0 bytes
Keys per prefix: 0
RawSize: 110.6 MB (estimated)
FileSize: 62.9 MB (estimated)
Write rate: 0 bytes/second
Compression: Snappy
Memtablerep: skip_list
Perf Level: 0
WARNING: Assertions are enabled; benchmarks unnecessarily slow
------------------------------------------------
DB path: [/tmp/rocksdbtest-112628/dbbench]
fillseq : 6.809 micros/op 146874 ops/sec; 16.2 MB/s
DB path: [/tmp/rocksdbtest-112628/dbbench]
readrandom : 6.343 micros/op 157665 ops/sec; 17.4 MB/s (1000000 of 1000000 found)
SIMULATOR CACHE STATISTICS:
SimCache LOOKUPs: 986559
SimCache HITs: 264760
SimCache HITRATE: 26.84%
[gzh@dev9927.prn1 ~/local/rocksdb] ./db_bench -benchmarks "fillseq,readrandom" -cache_size 1000000 -simcache_size 10000000
RocksDB: version 4.8
Date: Tue May 17 16:57:10 2016
CPU: 32 * Intel(R) Xeon(R) CPU E5-2660 0 @ 2.20GHz
CPUCache: 20480 KB
Keys: 16 bytes each
Values: 100 bytes each (50 bytes after compression)
Entries: 1000000
Prefix: 0 bytes
Keys per prefix: 0
RawSize: 110.6 MB (estimated)
FileSize: 62.9 MB (estimated)
Write rate: 0 bytes/second
Compression: Snappy
Memtablerep: skip_list
Perf Level: 0
WARNING: Assertions are enabled; benchmarks unnecessarily slow
------------------------------------------------
DB path: [/tmp/rocksdbtest-112628/dbbench]
fillseq : 5.066 micros/op 197394 ops/sec; 21.8 MB/s
DB path: [/tmp/rocksdbtest-112628/dbbench]
readrandom : 6.457 micros/op 154870 ops/sec; 17.1 MB/s (1000000 of 1000000 found)
SIMULATOR CACHE STATISTICS:
SimCache LOOKUPs: 1059764
SimCache HITs: 374501
SimCache HITRATE: 35.34%
[gzh@dev9927.prn1 ~/local/rocksdb] ./db_bench -benchmarks "fillseq,readrandom" -cache_size 1000000 -simcache_size 100000000
RocksDB: version 4.8
Date: Tue May 17 16:57:32 2016
CPU: 32 * Intel(R) Xeon(R) CPU E5-2660 0 @ 2.20GHz
CPUCache: 20480 KB
Keys: 16 bytes each
Values: 100 bytes each (50 bytes after compression)
Entries: 1000000
Prefix: 0 bytes
Keys per prefix: 0
RawSize: 110.6 MB (estimated)
FileSize: 62.9 MB (estimated)
Write rate: 0 bytes/second
Compression: Snappy
Memtablerep: skip_list
Perf Level: 0
WARNING: Assertions are enabled; benchmarks unnecessarily slow
------------------------------------------------
DB path: [/tmp/rocksdbtest-112628/dbbench]
fillseq : 5.632 micros/op 177572 ops/sec; 19.6 MB/s
DB path: [/tmp/rocksdbtest-112628/dbbench]
readrandom : 6.892 micros/op 145094 ops/sec; 16.1 MB/s (1000000 of 1000000 found)
SIMULATOR CACHE STATISTICS:
SimCache LOOKUPs: 1150767
SimCache HITs: 1034535
SimCache HITRATE: 89.90%
```
Reviewers: IslamAbdelRahman, andrewkr, sdong
Reviewed By: sdong
Subscribers: MarkCallaghan, andrewkr, dhruba, leveldb
Differential Revision: https://reviews.facebook.net/D57999
2016-05-23 23:35:23 -07:00