Make xf86PciVideoInfo static since it is only used within this file.
Dummy out all of the PCI bus and device access control functions. We need a better way to do this, and that will probably be in libpciaccess and / or the kernel. Refactor xf86GetPciInfoForEntity to use pci_device_find_by_slot. Refector xf86CheckPciSlot to use xf86GetPciEntity. Eliminate disablePciBios and the one place that calls it.
This commit is contained in:
parent
5508f7646f
commit
190f229ed7
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@ -54,7 +54,7 @@
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/* Bus-specific globals */
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Bool pciSlotClaimed = FALSE;
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struct pci_device ** xf86PciVideoInfo = NULL; /* PCI probe for video hw */
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static struct pci_device ** xf86PciVideoInfo = NULL; /* PCI probe for video hw */
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/* PCI classes that get included in xf86PciVideoInfo */
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@ -171,14 +171,14 @@ FindPCIVideoInfo(void)
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/* If we haven't found a primary device try a different heuristic */
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if (primaryBus.type == BUS_NONE && num) {
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for (i = 0; i < num; i++) {
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for (i = 0; i < num; i++) {
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uint16_t command;
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info = xf86PciVideoInfo[i];
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pci_device_cfg_read_u16( info, & command, 4 );
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pci_device_cfg_read_u16(info, & command, 4);
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if ( (command & PCI_CMD_MEM_ENABLE)
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&& ((num == 1) || IS_VGA( info->device_class )) ) {
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if ((command & PCI_CMD_MEM_ENABLE)
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&& ((num == 1) || IS_VGA(info->device_class))) {
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if (primaryBus.type == BUS_NONE) {
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primaryBus.type = BUS_PCI;
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primaryBus.id.pci.bus = PCI_MAKE_BUS( info->domain, info->bus );
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@ -206,7 +206,7 @@ FindPCIVideoInfo(void)
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chipname = pci_device_get_device_name( info );
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if ((!vendorname || !chipname) &&
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!PCIALWAYSPRINTCLASSES( info->device_class ))
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!PCIALWAYSPRINTCLASSES(info->device_class))
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continue;
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if (xf86IsPrimaryPci(info))
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@ -270,21 +270,25 @@ FindPCIVideoInfo(void)
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static void
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pciIoAccessEnable(void* arg)
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{
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#if 0
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#ifdef DEBUG
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ErrorF("pciIoAccessEnable: 0x%05lx\n", *(PCITAG *)arg);
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#endif
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pArg->ctrl |= SETBITS | PCI_CMD_MASTER_ENABLE;
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pci_device_cfg_write_u32( pArg->dev, & pArg->ctrl, PCI_CMD_STAT_REG );
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#endif
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}
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static void
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pciIoAccessDisable(void* arg)
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{
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#if 0
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#ifdef DEBUG
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ErrorF("pciIoAccessDisable: 0x%05lx\n", *(PCITAG *)arg);
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#endif
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pArg->ctrl &= ~SETBITS;
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pci_device_cfg_write_u32( pArg->dev, & pArg->ctrl, PCI_CMD_STAT_REG );
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#endif
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}
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#undef SETBITS
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@ -292,21 +296,25 @@ pciIoAccessDisable(void* arg)
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static void
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pciIo_MemAccessEnable(void* arg)
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{
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#if 0
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#ifdef DEBUG
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ErrorF("pciIo_MemAccessEnable: 0x%05lx\n", *(PCITAG *)arg);
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#endif
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pArg->ctrl |= SETBITS | PCI_CMD_MASTER_ENABLE;
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pci_device_cfg_write_u32( pArg->dev, & pArg->ctrl, PCI_CMD_STAT_REG );
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#endif
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}
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static void
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pciIo_MemAccessDisable(void* arg)
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{
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#if 0
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#ifdef DEBUG
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ErrorF("pciIo_MemAccessDisable: 0x%05lx\n", *(PCITAG *)arg);
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#endif
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pArg->ctrl &= ~SETBITS;
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pci_device_cfg_write_u32( pArg->dev, & pArg->ctrl, PCI_CMD_STAT_REG );
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#endif
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}
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#undef SETBITS
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@ -314,21 +322,25 @@ pciIo_MemAccessDisable(void* arg)
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static void
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pciMemAccessEnable(void* arg)
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{
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#if 0
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#ifdef DEBUG
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ErrorF("pciMemAccessEnable: 0x%05lx\n", *(PCITAG *)arg);
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#endif
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pArg->ctrl |= SETBITS | PCI_CMD_MASTER_ENABLE;
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pci_device_cfg_write_u32( pArg->dev, & pArg->ctrl, PCI_CMD_STAT_REG );
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#endif
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}
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static void
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pciMemAccessDisable(void* arg)
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{
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#if 0
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#ifdef DEBUG
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ErrorF("pciMemAccessDisable: 0x%05lx\n", *(PCITAG *)arg);
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#endif
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pArg->ctrl &= ~SETBITS;
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pci_device_cfg_write_u32( pArg->dev, & pArg->ctrl, PCI_CMD_STAT_REG );
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#endif
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}
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#undef SETBITS
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#undef pArg
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@ -339,6 +351,7 @@ pciMemAccessDisable(void* arg)
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static void
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pciBusAccessEnable(BusAccPtr ptr)
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{
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#if 0
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struct pci_device * const dev = ptr->busdep.pci.dev;
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uint16_t ctrl;
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@ -351,12 +364,14 @@ pciBusAccessEnable(BusAccPtr ptr)
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~(PCI_PCI_BRIDGE_MASTER_ABORT_EN | PCI_PCI_BRIDGE_SECONDARY_RESET);
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pci_device_cfg_write_u16( dev, & ctrl, PCI_PCI_BRIDGE_CONTROL_REG );
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}
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#endif
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}
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/* move to OS layer */
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static void
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pciBusAccessDisable(BusAccPtr ptr)
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{
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#if 0
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struct pci_device * const dev = ptr->busdep.pci.dev;
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uint16_t ctrl;
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@ -368,6 +383,7 @@ pciBusAccessDisable(BusAccPtr ptr)
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ctrl &= ~(MASKBITS | PCI_PCI_BRIDGE_SECONDARY_RESET);
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pci_device_cfg_write_u16( dev, & ctrl, PCI_PCI_BRIDGE_CONTROL_REG );
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}
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#endif
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}
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#undef MASKBITS
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@ -375,6 +391,7 @@ pciBusAccessDisable(BusAccPtr ptr)
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static void
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pciDrvBusAccessEnable(BusAccPtr ptr)
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{
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#if 0
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int bus = ptr->busdep.pci.bus;
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#ifdef DEBUG
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@ -383,12 +400,14 @@ pciDrvBusAccessEnable(BusAccPtr ptr)
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(*pciBusInfo[bus]->funcs->pciControlBridge)(bus,
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PCI_PCI_BRIDGE_VGA_EN,
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PCI_PCI_BRIDGE_VGA_EN);
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#endif
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}
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/* move to OS layer */
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static void
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pciDrvBusAccessDisable(BusAccPtr ptr)
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{
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#if 0
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int bus = ptr->busdep.pci.bus;
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#ifdef DEBUG
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#endif
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(*pciBusInfo[bus]->funcs->pciControlBridge)(bus,
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PCI_PCI_BRIDGE_VGA_EN, 0);
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#endif
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}
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static void
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pciSetBusAccess(BusAccPtr ptr)
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{
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#if 0
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#ifdef DEBUG
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ErrorF("pciSetBusAccess: route VGA to bus %d\n", ptr->busdep.pci.bus);
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#endif
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@ -424,12 +445,14 @@ pciSetBusAccess(BusAccPtr ptr)
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}
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ptr = ptr->primary;
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}
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#endif
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}
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/* move to OS layer */
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static void
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savePciState( struct pci_device * dev, pciSavePtr ptr )
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{
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#if 0
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int i;
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pci_device_cfg_read_u32( dev, & ptr->command, PCI_CMD_STAT_REG );
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}
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pci_device_cfg_read_u32( dev, & ptr->biosBase, PCI_CMD_BIOS_REG );
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#endif
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}
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/* move to OS layer */
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static void
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restorePciState( struct pci_device * dev, pciSavePtr ptr)
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{
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#if 0
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int i;
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/* disable card before setting anything */
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}
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pci_device_cfg_write_u32( dev, & ptr->command, PCI_CMD_STAT_REG );
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#endif
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}
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/* move to OS layer */
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static void
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savePciBusState(BusAccPtr ptr)
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{
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#if 0
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struct pci_device * const dev = ptr->busdep.pci.dev;
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uint16_t temp;
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temp = ptr->busdep.pci.save.control & ~PCI_PCI_BRIDGE_MASTER_ABORT_EN;
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pci_device_cfg_read_u16( dev, & temp, PCI_PCI_BRIDGE_CONTROL_REG );
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}
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#endif
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}
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/* move to OS layer */
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static void
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restorePciBusState(BusAccPtr ptr)
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{
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#if 0
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struct pci_device * const dev = ptr->busdep.pci.dev;
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uint16_t ctrl;
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ctrl |= ptr->busdep.pci.save.control & MASKBITS;
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pci_device_cfg_write_u16( dev, & ctrl, PCI_PCI_BRIDGE_CONTROL_REG );
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}
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#endif
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}
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#undef MASKBITS
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static void
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savePciDrvBusState(BusAccPtr ptr)
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{
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#if 0
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int bus = ptr->busdep.pci.bus;
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ptr->busdep.pci.save.control =
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(*pciBusInfo[bus]->funcs->pciControlBridge)(bus,
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PCI_PCI_BRIDGE_MASTER_ABORT_EN,
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0);
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#endif
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}
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/* move to OS layer */
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static void
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restorePciDrvBusState(BusAccPtr ptr)
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{
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#if 0
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int bus = ptr->busdep.pci.bus;
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(*pciBusInfo[bus]->funcs->pciControlBridge)(bus, (CARD16)(-1),
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ptr->busdep.pci.save.control);
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}
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static void
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disablePciBios(struct pci_device * dev)
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{
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pci_device_cfg_write_bits(dev, PCI_CMD_BIOS_ENABLE, 0,
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PCI_CMD_BIOS_REG);
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#endif
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}
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@ -688,6 +714,7 @@ initPciBusState(void)
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void
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PciStateEnter(void)
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{
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#if 0
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unsigned i;
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if (xf86PciVideoInfo == NULL)
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@ -702,11 +729,13 @@ PciStateEnter(void)
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paccp->arg.ctrl = paccp->restore.command;
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}
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}
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#endif
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}
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void
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PciBusStateEnter(void)
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{
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#if 0
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BusAccPtr pbap = xf86BusAccInfo;
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while (pbap) {
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@ -714,11 +743,13 @@ PciBusStateEnter(void)
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pbap->save_f(pbap);
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pbap = pbap->next;
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}
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#endif
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}
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void
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PciStateLeave(void)
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{
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#if 0
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unsigned i;
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if (xf86PciVideoInfo == NULL)
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@ -732,11 +763,13 @@ PciStateLeave(void)
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restorePciState(paccp->arg.dev, &paccp->save);
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}
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}
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#endif
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}
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void
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PciBusStateLeave(void)
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{
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#if 0
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BusAccPtr pbap = xf86BusAccInfo;
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while (pbap) {
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@ -744,11 +777,13 @@ PciBusStateLeave(void)
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pbap->restore_f(pbap);
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pbap = pbap->next;
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}
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#endif
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}
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void
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DisablePciAccess(void)
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{
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#if 0
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unsigned i;
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if (xf86PciVideoInfo == NULL)
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@ -761,11 +796,13 @@ DisablePciAccess(void)
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pciIo_MemAccessDisable(paccp->io_memAccess.arg);
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}
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}
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#endif
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}
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void
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DisablePciBusAccess(void)
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{
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#if 0
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BusAccPtr pbap = xf86BusAccInfo;
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while (pbap) {
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@ -775,6 +812,7 @@ DisablePciBusAccess(void)
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pbap->primary->current = NULL;
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pbap = pbap->next;
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}
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#endif
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}
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/*
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@ -825,8 +863,6 @@ xf86ClaimPciSlot(struct pci_device * d, DriverPtr drvp,
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pbap = pbap->next;
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}
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/* in case bios is enabled disable it */
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disablePciBios( d );
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pciSlotClaimed = TRUE;
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if (active) {
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@ -958,21 +994,12 @@ xf86GetPciInfoForEntity(int entityIndex)
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return NULL;
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p = xf86Entities[entityIndex];
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if (p->busType == BUS_PCI) {
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const unsigned domain = PCI_DOM_FROM_BUS(p->pciBusId.bus);
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const unsigned bus = PCI_BUS_NO_DOMAIN(p->pciBusId.bus);
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struct pci_device ** ppPci;
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for (ppPci = xf86PciVideoInfo; *ppPci != NULL; ppPci++) {
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if (domain == (*ppPci)->domain &&
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bus == (*ppPci)->bus &&
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p->pciBusId.device == (*ppPci)->dev &&
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p->pciBusId.func == (*ppPci)->func)
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return (*ppPci);
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}
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}
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return NULL;
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return (p->busType == BUS_PCI)
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? pci_device_find_by_slot(PCI_DOM_FROM_BUS(p->pciBusId.bus),
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PCI_BUS_NO_DOMAIN(p->pciBusId.bus),
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p->pciBusId.device,
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p->pciBusId.func)
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: NULL;
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}
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_X_EXPORT int
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@ -981,13 +1008,14 @@ xf86GetPciEntity(int bus, int dev, int func)
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int i;
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for (i = 0; i < xf86NumEntities; i++) {
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EntityPtr p = xf86Entities[i];
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if (p->busType != BUS_PCI) continue;
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if (p->pciBusId.bus == bus &&
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p->pciBusId.device == dev &&
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p->pciBusId.func == func)
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const EntityPtr p = xf86Entities[i];
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if ((p->busType == BUS_PCI) &&
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(p->pciBusId.bus == bus) &&
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(p->pciBusId.device == dev) &&
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(p->pciBusId.func == func)) {
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return i;
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}
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}
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return -1;
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}
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@ -1014,19 +1042,8 @@ xf86CheckPciMemBase( struct pci_device * pPci, memType base )
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_X_EXPORT Bool
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xf86CheckPciSlot( const struct pci_device * d )
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{
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int i;
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EntityPtr p;
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const unsigned busnum = PCI_MAKE_BUS(d->domain, d->bus);
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for (i = 0; i < xf86NumEntities; i++) {
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p = xf86Entities[i];
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/* Check if this PCI slot is taken */
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if (p->busType == BUS_PCI && p->pciBusId.bus == busnum &&
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p->pciBusId.device == d->dev && p->pciBusId.func == d->func)
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return FALSE;
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}
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return TRUE;
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return (xf86GetPciEntity(PCI_MAKE_BUS(d->domain, d->bus),
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d->dev, d->func) == -1);
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}
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