Remove pciConfigPtr and all of the associated cruft.
This commit is contained in:
Ian Romanick
parent
966ebd3d2d
commit
23f44df900
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@ -57,7 +57,7 @@ ScanPciDisplayPCICardInfo(void)
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xf86EnableIO();
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if (xf86scanpci(0) == NULL) {
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if (! xf86scanpci()) {
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xf86MsgVerb(X_NONE, 0, "No PCI info available\n");
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return;
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}
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@ -54,7 +54,6 @@
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/* Bus-specific globals */
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Bool pciSlotClaimed = FALSE;
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static pciConfigPtr *xf86PciInfo = NULL; /* Full PCI probe info */
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struct pci_device ** xf86PciVideoInfo = NULL; /* PCI probe for video hw */
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@ -133,9 +132,7 @@ FindPCIVideoInfo(void)
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struct pci_device_iterator * iter;
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xf86PciInfo = xf86scanpci(0);
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if (xf86PciInfo == NULL) {
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if (!xf86scanpci()) {
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xf86PciVideoInfo = NULL;
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return;
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}
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@ -220,8 +220,6 @@ pciBusInfo_t *pciBusInfo[MAX_PCI_BUSES] = { NULL, };
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_X_EXPORT int pciNumBuses = 0; /* Actual number of PCI buses */
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int pciMaxBusNum = MAX_PCI_BUSES;
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static pciConfigPtr pci_devp[MAX_PCI_DEVICES + 1] = {NULL, };
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/*
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* pciInit - choose correct platform/OS specific PCI init routine
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@ -304,166 +302,26 @@ pciAddrNOOP(PCITAG tag, PciAddrType type, ADDRESS addr)
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return(addr);
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}
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_X_EXPORT pciConfigPtr *
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xf86scanpci(int flags)
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_X_EXPORT Bool
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xf86scanpci(void)
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{
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pciConfigPtr devp;
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pciBusInfo_t *busp;
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int idx = 0, i;
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struct pci_device * dev;
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struct pci_device_iterator * iter;
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static Bool done = FALSE;
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static Bool success = FALSE;
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/*
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* if we haven't found PCI devices checking for pci_devp may
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* result in an endless recursion if platform/OS specific PCI
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* bus probing code calls this function from with in it.
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*/
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if (done || pci_devp[0])
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return pci_devp;
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if (done)
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return success;
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done = TRUE;
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pci_system_init();
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success = (pci_system_init() == 0);
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pciInit();
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#ifdef XF86SCANPCI_WRAPPER
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XF86SCANPCI_WRAPPER(SCANPCI_INIT);
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#endif
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iter = pci_slot_match_iterator_create(NULL);
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dev = pci_device_next(iter);
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/* Check if no devices, return now */
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if (dev == NULL) {
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#ifdef XF86SCANPCI_WRAPPER
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XF86SCANPCI_WRAPPER(SCANPCI_TERM);
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#endif
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return NULL;
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}
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while ((idx < MAX_PCI_DEVICES) && (dev != NULL)) {
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pci_device_probe(dev);
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devp = xcalloc(1, sizeof(pciDevice));
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if (!devp) {
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xf86Msg(X_ERROR,
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"xf86scanpci: Out of memory after %d devices!!\n", idx);
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return (pciConfigPtr *)NULL;
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}
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/* Identify pci device by bus, dev, func, and tag */
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devp->dev = dev;
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devp->busnum = PCI_MAKE_BUS(dev->domain, dev->bus);
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devp->devnum = dev->dev;
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devp->funcnum = dev->func;
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devp->tag = PCI_MAKE_TAG(devp->busnum, dev->dev, dev->func);
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/* Read config space for this device */
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for (i = 0; i < 17; i++) { /* PCI hdr plus 1st dev spec dword */
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pci_device_cfg_read_u32(dev, & devp->cfgspc.dwords[i],
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i * sizeof(CARD32));
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}
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/* Some broken devices don't implement this field... */
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if (devp->pci_header_type == 0xff)
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devp->pci_header_type = 0;
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switch (devp->pci_header_type & 0x7f) {
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case 0:
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break;
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case 1:
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case 2: {
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const uint8_t control = devp->pci_bridge_control &
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~(PCI_PCI_BRIDGE_MASTER_ABORT_EN |
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PCI_PCI_BRIDGE_SECONDARY_RESET);
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/* Allow master aborts to complete normally on secondary buses */
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if (!(devp->pci_bridge_control & PCI_PCI_BRIDGE_MASTER_ABORT_EN))
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break;
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pci_device_cfg_write_u8(dev, & control,
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PCI_PCI_BRIDGE_CONTROL_REG);
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break;
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}
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default:
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break;
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}
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xf86MsgVerb(X_INFO, 2, "PCI: %.2x:%02x:%1x: chip %04x,%04x"
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" card %04x,%04x rev %02x class %02x,%02x,%02x hdr %02x\n",
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devp->busnum, devp->devnum, devp->funcnum,
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devp->pci_vendor, devp->_pci_device,
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devp->pci_subsys_vendor, devp->pci_subsys_card,
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devp->pci_rev_id, devp->pci_base_class,
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devp->pci_sub_class, devp->pci_prog_if,
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devp->pci_header_type);
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pci_devp[idx++] = devp;
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dev = pci_device_next(iter);
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}
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/* Restore modified data (in reverse order), and link buses */
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while (--idx >= 0) {
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devp = pci_devp[idx];
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switch (devp->pci_header_type & 0x7f) {
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case 0:
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if ((devp->pci_base_class != PCI_CLASS_BRIDGE) ||
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(devp->pci_sub_class != PCI_SUBCLASS_BRIDGE_HOST))
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break;
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pciBusInfo[devp->busnum]->bridge = devp;
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pciBusInfo[devp->busnum]->primary_bus = devp->busnum;
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break;
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case 1:
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case 2: {
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uint8_t control;
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i = PCI_SECONDARY_BUS_EXTRACT(devp->pci_pp_bus_register, devp->tag);
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if (i > devp->busnum) {
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if (pciBusInfo[i]) {
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pciBusInfo[i]->bridge = devp;
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}
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#ifdef ARCH_PCI_PCI_BRIDGE
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ARCH_PCI_PCI_BRIDGE(devp);
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#endif
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}
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if (!(devp->pci_bridge_control & PCI_PCI_BRIDGE_MASTER_ABORT_EN))
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break;
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control = devp->pci_bridge_control & ~PCI_PCI_BRIDGE_SECONDARY_RESET;
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pci_device_cfg_write_u8(devp->dev, & control,
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PCI_PCI_BRIDGE_CONTROL_REG);
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break;
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}
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default:
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break;
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}
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}
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#ifdef XF86SCANPCI_WRAPPER
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XF86SCANPCI_WRAPPER(SCANPCI_TERM);
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#endif
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xf86MsgVerb(X_INFO, 2, "PCI: End of PCI scan\n");
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return pci_devp;
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}
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pciConfigPtr
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xf86GetPciConfigFromTag(PCITAG Tag)
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{
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pciConfigPtr pDev;
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int i = 0;
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for (i = 0 ; (pDev = pci_devp[i]) && i <= MAX_PCI_DEVICES; i++) {
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if (Tag == pDev->tag)
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return pDev;
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}
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return NULL; /* Bad data */
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return success;
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}
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#ifdef INCLUDE_XF86_NO_DOMAIN
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@ -156,38 +156,6 @@
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#define PCI_BUS_NO_DOMAIN(bus) ((bus) & 0xffu)
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#define PCI_TAG_NO_DOMAIN(tag) ((tag) & 0x00ffff00u)
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/*
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* Macros for bus numbers found in P2P headers.
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*/
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#define PCI_PRIMARY_BUS_EXTRACT(x, tag) \
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((((x) & PCI_PRIMARY_BUS_MASK ) >> 0) | (PCI_DOM_FROM_TAG(tag) << 8))
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#define PCI_SECONDARY_BUS_EXTRACT(x, tag) \
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((((x) & PCI_SECONDARY_BUS_MASK ) >> 8) | (PCI_DOM_FROM_TAG(tag) << 8))
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#define PCI_SUBORDINATE_BUS_EXTRACT(x, tag) \
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((((x) & PCI_SUBORDINATE_BUS_MASK) >> 16) | (PCI_DOM_FROM_TAG(tag) << 8))
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#define PCI_PRIMARY_BUS_INSERT(x, y) \
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(((x) & ~PCI_PRIMARY_BUS_MASK ) | (((y) & 0xffu) << 0))
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#define PCI_SECONDARY_BUS_INSERT(x, y) \
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(((x) & ~PCI_SECONDARY_BUS_MASK ) | (((y) & 0xffu) << 8))
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#define PCI_SUBORDINATE_BUS_INSERT(x, y) \
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(((x) & ~PCI_SUBORDINATE_BUS_MASK) | (((y) & 0xffu) << 16))
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/* Ditto for CardBus bridges */
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#define PCI_CB_PRIMARY_BUS_EXTRACT(x, tag) \
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PCI_PRIMARY_BUS_EXTRACT(x, tag)
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#define PCI_CB_CARDBUS_BUS_EXTRACT(x, tag) \
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PCI_SECONDARY_BUS_EXTRACT(x, tag)
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#define PCI_CB_SUBORDINATE_BUS_EXTRACT(x, tag) \
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PCI_SUBORDINATE_BUS_EXTRACT(x, tag)
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#define PCI_CB_PRIMARY_BUS_INSERT(x, tag) \
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PCI_PRIMARY_BUS_INSERT(x, tag)
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#define PCI_CB_CARDBUS_BUS_INSERT(x, tag) \
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PCI_SECONDARY_BUS_INSERT(x, tag)
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#define PCI_CB_SUBORDINATE_BUS_INSERT(x, tag) \
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PCI_SUBORDINATE_BUS_INSERT(x, tag)
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#if X_BYTE_ORDER == X_BIG_ENDIAN
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#define PCI_CPU(val) (((val >> 24) & 0x000000ff) | \
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((val >> 8) & 0x0000ff00) | \
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@ -352,10 +320,6 @@ extern void ARCH_PCI_INIT(void);
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extern void ARCH_PCI_OS_INIT(void);
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#endif
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#if defined(ARCH_PCI_PCI_BRIDGE)
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extern void ARCH_PCI_PCI_BRIDGE(pciConfigPtr pPCI);
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#endif
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#if defined(XF86SCANPCI_WRAPPER)
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typedef enum {
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SCANPCI_INIT,
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@ -402,7 +366,7 @@ typedef struct pci_bus_info {
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int primary_bus; /* Parent bus */
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pciBusFuncs_p funcs; /* PCI access functions */
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void *pciBusPriv; /* Implementation private data */
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pciConfigPtr bridge; /* bridge that opens this bus */
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struct pci_device *bridge; /* bridge that opens this bus */
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} pciBusInfo_t;
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#define HOST_NO_BUS ((pciBusInfo_t *)(-1))
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@ -129,69 +129,71 @@ linuxPciInit()
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pciBusInfo[0] = &linuxPci0;
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}
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/**
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* \bug
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* The generation of the procfs for the domain != 0 case may not be correct.
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*/
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static int
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linuxPciOpenFile(PCITAG tag, Bool write)
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linuxPciOpenFile(struct pci_device *dev, Bool write)
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{
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static int lbus,ldev,lfunc,fd = -1,is_write = 0;
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int bus, dev, func;
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char file[64];
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struct stat ignored;
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static int is26 = -1;
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static struct pci_device *last_dev = NULL;
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static int fd = -1,is_write = 0;
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char file[64];
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struct stat ignored;
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static int is26 = -1;
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bus = PCI_BUS_FROM_TAG(tag);
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dev = PCI_DEV_FROM_TAG(tag);
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func = PCI_FUNC_FROM_TAG(tag);
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if (is26 == -1) {
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if (stat("/sys/bus/pci",&ignored) < 0)
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is26 = 0;
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else
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is26 = 1;
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}
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if (is26 == -1) {
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is26 = (stat("/sys/bus/pci", &ignored) < 0) ? 0 : 1;
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}
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if (fd == -1 || (write && (!is_write))
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|| bus != lbus || dev != ldev || func != lfunc) {
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if (fd != -1)
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close(fd);
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if (is26)
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sprintf(file,"/sys/bus/pci/devices/0000:%02x:%02x.%01x/config",
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bus, dev, func);
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else {
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if (bus < 256) {
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sprintf(file,"/proc/bus/pci/%02x",bus);
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if (stat(file, &ignored) < 0)
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sprintf(file, "/proc/bus/pci/0000:%02x/%02x.%1x",
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bus, dev, func);
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else
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sprintf(file, "/proc/bus/pci/%02x/%02x.%1x",
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bus, dev, func);
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} else {
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sprintf(file,"/proc/bus/pci/%04x",bus);
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if (stat(file, &ignored) < 0)
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sprintf(file, "/proc/bus/pci/0000:%04x/%02x.%1x",
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bus, dev, func);
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else
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sprintf(file, "/proc/bus/pci/%04x/%02x.%1x",
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bus, dev, func);
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}
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if (fd == -1 || (write && (!is_write)) || (last_dev != dev)) {
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if (fd != -1)
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close(fd);
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if (is26) {
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sprintf(file,"/sys/bus/pci/devices/%04u:%02x:%02x.%01x/config",
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dev->domain, dev->bus, dev->dev, dev->func);
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} else {
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if (dev->domain == 0) {
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sprintf(file,"/proc/bus/pci/%02x", dev->bus);
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if (stat(file, &ignored) < 0) {
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sprintf(file, "/proc/bus/pci/0000:%02x/%02x.%1x",
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dev->bus, dev->dev, dev->func);
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} else {
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sprintf(file, "/proc/bus/pci/%02x/%02x.%1x",
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dev->bus, dev->dev, dev->func);
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}
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if (write) {
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fd = open(file,O_RDWR);
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if (fd != -1) is_write = TRUE;
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} else switch (is_write) {
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case TRUE:
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fd = open(file,O_RDWR);
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if (fd > -1)
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break;
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default:
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fd = open(file,O_RDONLY);
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is_write = FALSE;
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} else {
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sprintf(file,"/proc/bus/pci/%02x%02x", dev->domain, dev->bus);
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if (stat(file, &ignored) < 0) {
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sprintf(file, "/proc/bus/pci/%04x:%04x/%02x.%1x",
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dev->domain, dev->bus, dev->dev, dev->func);
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} else {
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sprintf(file, "/proc/bus/pci/%02x%02x/%02x.%1x",
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dev->domain, dev->bus, dev->dev, dev->func);
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}
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lbus = bus;
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ldev = dev;
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lfunc = func;
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}
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}
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return fd;
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if (write) {
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fd = open(file,O_RDWR);
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if (fd != -1) is_write = TRUE;
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} else {
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switch (is_write) {
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case TRUE:
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fd = open(file,O_RDWR);
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if (fd > -1)
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break;
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default:
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fd = open(file,O_RDONLY);
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is_write = FALSE;
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}
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}
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last_dev = dev;
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}
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return fd;
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}
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static CARD32
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@ -397,7 +399,7 @@ linuxPciCfgWriteWord(PCITAG tag, int off, CARD16 val)
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#endif
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/* This probably shouldn't be Linux-specific */
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static pciConfigPtr
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static struct pci_device *
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xf86GetPciHostConfigFromTag(PCITAG Tag)
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{
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int bus = PCI_BUS_FROM_TAG(Tag);
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@ -483,18 +485,18 @@ linuxGetIOSize(PCITAG Tag)
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_X_EXPORT int
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xf86GetPciDomain(PCITAG Tag)
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{
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pciConfigPtr pPCI;
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const struct pci_device *dev;
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int fd, result;
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pPCI = xf86GetPciHostConfigFromTag(Tag);
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dev = xf86GetPciHostConfigFromTag(Tag);
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if (pPCI && (result = PCI_DOM_FROM_BUS(pPCI->busnum)))
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return result;
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if (!pPCI)
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if (!dev)
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return 1; /* Domain 0 is reserved */
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if ((fd = linuxPciOpenFile(pPCI->tag, FALSE)) < 0)
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if ((result = PCI_DOM_FROM_TAG(Tag)) != 0)
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return result;
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if ((fd = linuxPciOpenFile(Tag, FALSE)) < 0)
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return 0;
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if ((result = ioctl(fd, PCIIOC_CONTROLLER, 0)) < 0)
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@ -508,16 +510,18 @@ linuxMapPci(int ScreenNum, int Flags, PCITAG Tag,
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ADDRESS Base, unsigned long Size, int mmap_ioctl)
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{
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do {
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pciConfigPtr pPCI;
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struct pci_device *dev;
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unsigned char *result;
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ADDRESS realBase, Offset;
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int fd, mmapflags, prot;
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xf86InitVidMem();
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pPCI = xf86GetPciHostConfigFromTag(Tag);
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dev = xf86GetPciHostConfigFromTag(Tag);
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if (((fd = linuxPciOpenFile(pPCI ? pPCI->tag : 0,FALSE)) < 0) ||
|
||||
/* FIXME: What if dev == NULL? */
|
||||
|
||||
if (((fd = linuxPciOpenFile(dev, FALSE)) < 0) ||
|
||||
(ioctl(fd, mmap_ioctl, 0) < 0))
|
||||
break;
|
||||
|
||||
|
|
@ -578,41 +582,39 @@ static pointer DomainMmappedMem[MAX_DOMAINS];
|
|||
|
||||
static int
|
||||
linuxOpenLegacy(PCITAG Tag, char *name)
|
||||
|
||||
{
|
||||
#define PREFIX "/sys/class/pci_bus/%04x:%02x/%s"
|
||||
char *path;
|
||||
int domain, bus;
|
||||
pciBusInfo_t *pBusInfo;
|
||||
pciConfigPtr bridge = NULL;
|
||||
struct pci_device *dev;
|
||||
int fd;
|
||||
|
||||
path = xalloc(strlen(PREFIX) + strlen(name));
|
||||
if (!path)
|
||||
return -1;
|
||||
|
||||
for (;;) {
|
||||
domain = xf86GetPciDomain(Tag);
|
||||
bus = PCI_BUS_NO_DOMAIN(PCI_BUS_FROM_TAG(Tag));
|
||||
|
||||
/* Domain 0 is reserved -- see xf86GetPciDomain() */
|
||||
if ((domain <= 0) || (domain >= MAX_DOMAINS))
|
||||
FatalError("linuxOpenLegacy(): domain out of range\n");
|
||||
|
||||
sprintf(path, PREFIX, domain - 1, bus, name);
|
||||
dev = pci_device_find_by_slot(PCI_DOM_FROM_TAG(Tag),
|
||||
PCI_BUS_NO_DOM(PCI_BUS_FROM_TAG(Tag)),
|
||||
PCI_DEV_FROM_TAG(Tag),
|
||||
PCI_FUNC_FROM_TAG(Tag));
|
||||
while (dev != NULL) {
|
||||
sprintf(path, PREFIX, dev->domain, dev->bus, name);
|
||||
fd = open(path, O_RDWR);
|
||||
if (fd >= 0) {
|
||||
xfree(path);
|
||||
return fd;
|
||||
}
|
||||
|
||||
pBusInfo = pciBusInfo[bus];
|
||||
pBusInfo = pciBusInfo[PCI_MAKE_BUS(dev->domain, dev->bus)];
|
||||
if (!pBusInfo || (bridge == pBusInfo->bridge) ||
|
||||
!(bridge = pBusInfo->bridge)) {
|
||||
!pBusInfo->bridge) {
|
||||
xfree(path);
|
||||
return -1;
|
||||
}
|
||||
|
||||
Tag = bridge->tag;
|
||||
dev = pBusInfo->bridge;
|
||||
}
|
||||
|
||||
xfree(path);
|
||||
|
|
|
|||
|
|
@ -107,8 +107,6 @@
|
|||
#include <X11/Xfuncproto.h>
|
||||
#include "misc.h"
|
||||
|
||||
#define PCI_NOT_FOUND 0xFFFFFFFFU
|
||||
|
||||
/*
|
||||
* PCI cfg space definitions (e.g. stuff right out of the PCI spec)
|
||||
*/
|
||||
|
|
@ -172,19 +170,6 @@
|
|||
#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00
|
||||
#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01
|
||||
|
||||
/* 0x01 mass storage subclasses */
|
||||
#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00
|
||||
#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01
|
||||
#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02
|
||||
#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03
|
||||
#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80
|
||||
|
||||
/* 0x02 network subclasses */
|
||||
#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00
|
||||
#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01
|
||||
#define PCI_SUBCLASS_NETWORK_FDDI 0x02
|
||||
#define PCI_SUBCLASS_NETWORK_MISC 0x80
|
||||
|
||||
/* 0x03 display subclasses */
|
||||
#define PCI_SUBCLASS_DISPLAY_VGA 0x00
|
||||
#define PCI_SUBCLASS_DISPLAY_XGA 0x01
|
||||
|
|
@ -195,11 +180,6 @@
|
|||
#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01
|
||||
#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80
|
||||
|
||||
/* 0x05 memory subclasses */
|
||||
#define PCI_SUBCLASS_MEMORY_RAM 0x00
|
||||
#define PCI_SUBCLASS_MEMORY_FLASH 0x01
|
||||
#define PCI_SUBCLASS_MEMORY_MISC 0x80
|
||||
|
||||
/* 0x06 bridge subclasses */
|
||||
#define PCI_SUBCLASS_BRIDGE_HOST 0x00
|
||||
#define PCI_SUBCLASS_BRIDGE_ISA 0x01
|
||||
|
|
@ -213,33 +193,6 @@
|
|||
#define PCI_SUBCLASS_BRIDGE_MISC 0x80
|
||||
#define PCI_IF_BRIDGE_PCI_SUBTRACTIVE 0x01
|
||||
|
||||
/* 0x07 communications controller subclasses */
|
||||
#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00
|
||||
#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01
|
||||
#define PCI_SUBCLASS_COMMUNICATIONS_MULTISERIAL 0x02
|
||||
#define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03
|
||||
#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80
|
||||
|
||||
/* 0x08 generic system peripherals subclasses */
|
||||
#define PCI_SUBCLASS_SYSPERIPH_PIC 0x00
|
||||
#define PCI_SUBCLASS_SYSPERIPH_DMA 0x01
|
||||
#define PCI_SUBCLASS_SYSPERIPH_TIMER 0x02
|
||||
#define PCI_SUBCLASS_SYSPERIPH_RTC 0x03
|
||||
#define PCI_SUBCLASS_SYSPERIPH_HOTPCI 0x04
|
||||
#define PCI_SUBCLASS_SYSPERIPH_MISC 0x80
|
||||
|
||||
/* 0x09 input device subclasses */
|
||||
#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00
|
||||
#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01
|
||||
#define PCI_SUBCLASS_INPUT_MOUSE 0x02
|
||||
#define PCI_SUBCLASS_INPUT_SCANNER 0x03
|
||||
#define PCI_SUBCLASS_INPUT_GAMEPORT 0x04
|
||||
#define PCI_SUBCLASS_INPUT_MISC 0x80
|
||||
|
||||
/* 0x0a docking station subclasses */
|
||||
#define PCI_SUBCLASS_DOCKING_GENERIC 0x00
|
||||
#define PCI_SUBCLASS_DOCKING_MISC 0x80
|
||||
|
||||
/* 0x0b processor subclasses */
|
||||
#define PCI_SUBCLASS_PROCESSOR_386 0x00
|
||||
#define PCI_SUBCLASS_PROCESSOR_486 0x01
|
||||
|
|
@ -249,101 +202,6 @@
|
|||
#define PCI_SUBCLASS_PROCESSOR_MIPS 0x30
|
||||
#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40
|
||||
|
||||
/* 0x0c serial bus controller subclasses */
|
||||
#define PCI_SUBCLASS_SERIAL_FIREWIRE 0x00
|
||||
#define PCI_SUBCLASS_SERIAL_ACCESS 0x01
|
||||
#define PCI_SUBCLASS_SERIAL_SSA 0x02
|
||||
#define PCI_SUBCLASS_SERIAL_USB 0x03
|
||||
#define PCI_SUBCLASS_SERIAL_FIBRECHANNEL 0x04
|
||||
#define PCI_SUBCLASS_SERIAL_SMBUS 0x05
|
||||
|
||||
/* 0x0d wireless controller subclasses */
|
||||
#define PCI_SUBCLASS_WIRELESS_IRDA 0x00
|
||||
#define PCI_SUBCLASS_WIRELESS_CONSUMER_IR 0x01
|
||||
#define PCI_SUBCLASS_WIRELESS_RF 0x02
|
||||
#define PCI_SUBCLASS_WIRELESS_MISC 0x80
|
||||
|
||||
/* 0x0e intelligent I/O controller subclasses */
|
||||
#define PCI_SUBCLASS_I2O_I2O 0x00
|
||||
|
||||
/* 0x0f satellite communications controller subclasses */
|
||||
#define PCI_SUBCLASS_SATELLITE_TV 0x01
|
||||
#define PCI_SUBCLASS_SATELLITE_AUDIO 0x02
|
||||
#define PCI_SUBCLASS_SATELLITE_VOICE 0x03
|
||||
#define PCI_SUBCLASS_SATELLITE_DATA 0x04
|
||||
|
||||
/* 0x10 encryption/decryption controller subclasses */
|
||||
#define PCI_SUBCLASS_CRYPT_NET_COMPUTING 0x00
|
||||
#define PCI_SUBCLASS_CRYPT_ENTERTAINMENT 0x10
|
||||
#define PCI_SUBCLASS_CRYPT_MISC 0x80
|
||||
|
||||
/* 0x11 data acquisition and signal processing controller subclasses */
|
||||
#define PCI_SUBCLASS_DATAACQ_DPIO 0x00
|
||||
#define PCI_SUBCLASS_DATAACQ_MISC 0x80
|
||||
|
||||
|
||||
/* Header */
|
||||
#define PCI_HEADER_MISC 0x0c
|
||||
#define PCI_HEADER_MULTIFUNCTION 0x00800000
|
||||
|
||||
/* Interrupt configration register */
|
||||
#define PCI_INTERRUPT_REG 0x3c
|
||||
#define PCI_INTERRUPT_PIN_MASK 0x0000ff00
|
||||
#define PCI_INTERRUPT_PIN_EXTRACT(x) \
|
||||
((((x) & PCI_INTERRUPT_PIN_MASK) >> 8) & 0xff)
|
||||
#define PCI_INTERRUPT_PIN_NONE 0x00
|
||||
#define PCI_INTERRUPT_PIN_A 0x01
|
||||
#define PCI_INTERRUPT_PIN_B 0x02
|
||||
#define PCI_INTERRUPT_PIN_C 0x03
|
||||
#define PCI_INTERRUPT_PIN_D 0x04
|
||||
|
||||
#define PCI_INTERRUPT_LINE_MASK 0x000000ff
|
||||
#define PCI_INTERRUPT_LINE_EXTRACT(x) \
|
||||
((((x) & PCI_INTERRUPT_LINE_MASK) >> 0) & 0xff)
|
||||
#define PCI_INTERRUPT_LINE_INSERT(x,v) \
|
||||
(((x) & ~PCI_INTERRUPT_LINE_MASK) | ((v) << 0))
|
||||
|
||||
/* Base registers */
|
||||
#define PCI_MAP_REG_START 0x10
|
||||
#define PCI_MAP_REG_END 0x28
|
||||
#define PCI_MAP_ROM_REG 0x30
|
||||
|
||||
#define PCI_MAP_MEMORY 0x00000000
|
||||
#define PCI_MAP_IO 0x00000001
|
||||
|
||||
#define PCI_MAP_MEMORY_TYPE 0x00000007
|
||||
#define PCI_MAP_IO_TYPE 0x00000003
|
||||
|
||||
#define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000
|
||||
#define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002
|
||||
#define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004
|
||||
#define PCI_MAP_MEMORY_TYPE_MASK 0x00000006
|
||||
#define PCI_MAP_MEMORY_CACHABLE 0x00000008
|
||||
#define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e
|
||||
#define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0
|
||||
|
||||
#define PCI_MAP_IO_ATTR_MASK 0x00000003
|
||||
|
||||
#define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO)
|
||||
#define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b))
|
||||
|
||||
#define PCI_MAP_IS64BITMEM(b) \
|
||||
(((b) & PCI_MAP_MEMORY_TYPE) == PCI_MAP_MEMORY_TYPE_64BIT)
|
||||
|
||||
#define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK)
|
||||
#define PCIGETMEMORY64HIGH(b) (*((CARD32*)&(b) + 1))
|
||||
#define PCIGETMEMORY64(b) \
|
||||
(PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32))
|
||||
|
||||
#define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc
|
||||
|
||||
#define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK)
|
||||
|
||||
#define PCI_MAP_ROM_DECODE_ENABLE 0x00000001
|
||||
#define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800
|
||||
|
||||
#define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK)
|
||||
|
||||
/* PCI-PCI bridge mapping registers */
|
||||
#define PCI_PCI_BRIDGE_BUS_REG 0x18
|
||||
#define PCI_SUBORDINATE_BUS_MASK 0x00ff0000
|
||||
|
|
@ -354,12 +212,6 @@
|
|||
#define PCI_PCI_BRIDGE_MEM_REG 0x20
|
||||
#define PCI_PCI_BRIDGE_PMEM_REG 0x24
|
||||
|
||||
#define PCI_PPB_IOBASE_EXTRACT(x) (((x) << 8) & 0xFF00)
|
||||
#define PCI_PPB_IOLIMIT_EXTRACT(x) (((x) << 0) & 0xFF00)
|
||||
|
||||
#define PCI_PPB_MEMBASE_EXTRACT(x) (((x) << 16) & 0xFFFF0000)
|
||||
#define PCI_PPB_MEMLIMIT_EXTRACT(x) (((x) << 0) & 0xFFFF0000)
|
||||
|
||||
#define PCI_PCI_BRIDGE_CONTROL_REG 0x3E
|
||||
#define PCI_PCI_BRIDGE_PARITY_EN 0x01
|
||||
#define PCI_PCI_BRIDGE_SERR_EN 0x02
|
||||
|
|
@ -368,31 +220,6 @@
|
|||
#define PCI_PCI_BRIDGE_MASTER_ABORT_EN 0x20
|
||||
#define PCI_PCI_BRIDGE_SECONDARY_RESET 0x40
|
||||
#define PCI_PCI_BRIDGE_FAST_B2B_EN 0x80
|
||||
/* header type 2 extensions */
|
||||
#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
|
||||
#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
|
||||
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100
|
||||
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
|
||||
#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
|
||||
|
||||
#define PCI_CB_SEC_STATUS_REG 0x16 /* Secondary status */
|
||||
#define PCI_CB_PRIMARY_BUS_REG 0x18 /* PCI bus number */
|
||||
#define PCI_CB_CARD_BUS_REG 0x19 /* CardBus bus number */
|
||||
#define PCI_CB_SUBORDINATE_BUS_REG 0x1a /* Subordinate bus number */
|
||||
#define PCI_CB_LATENCY_TIMER_REG 0x1b /* CardBus latency timer */
|
||||
#define PCI_CB_MEM_BASE_0_REG 0x1c
|
||||
#define PCI_CB_MEM_LIMIT_0_REG 0x20
|
||||
#define PCI_CB_MEM_BASE_1_REG 0x24
|
||||
#define PCI_CB_MEM_LIMIT_1_REG 0x28
|
||||
#define PCI_CB_IO_BASE_0_REG 0x2c
|
||||
#define PCI_CB_IO_LIMIT_0_REG 0x30
|
||||
#define PCI_CB_IO_BASE_1_REG 0x34
|
||||
#define PCI_CB_IO_LIMIT_1_REG 0x38
|
||||
#define PCI_CB_BRIDGE_CONTROL_REG 0x3E
|
||||
|
||||
#define PCI_CB_IO_RANGE_MASK ~0x03
|
||||
#define PCI_CB_IOBASE(x) (x & PCI_CB_IO_RANGE_MASK)
|
||||
#define PCI_CB_IOLIMIT(x) ((x & PCI_CB_IO_RANGE_MASK) + 3)
|
||||
|
||||
/* Subsystem identification register */
|
||||
#define PCI_SUBSYSTEM_ID_REG 0x2c
|
||||
|
|
@ -410,255 +237,6 @@ typedef unsigned long ADDRESS; /* Memory/PCI address */
|
|||
typedef unsigned long IOADDRESS; /* Must be large enough for a pointer */
|
||||
typedef unsigned long PCITAG;
|
||||
|
||||
/*
|
||||
* PCI configuration space
|
||||
*/
|
||||
typedef struct pci_cfg_regs {
|
||||
/* start of official PCI config space header */
|
||||
union { /* Offset 0x0 - 0x3 */
|
||||
CARD32 device_vendor;
|
||||
struct {
|
||||
#if X_BYTE_ORDER == X_BIG_ENDIAN
|
||||
CARD16 device;
|
||||
CARD16 vendor;
|
||||
#else
|
||||
CARD16 vendor;
|
||||
CARD16 device;
|
||||
#endif
|
||||
} dv;
|
||||
} dv_id;
|
||||
|
||||
union { /* Offset 0x4 - 0x8 */
|
||||
CARD32 status_command;
|
||||
struct {
|
||||
#if X_BYTE_ORDER == X_BIG_ENDIAN
|
||||
CARD16 status;
|
||||
CARD16 command;
|
||||
#else
|
||||
CARD16 command;
|
||||
CARD16 status;
|
||||
#endif
|
||||
} sc;
|
||||
} stat_cmd;
|
||||
|
||||
union { /* Offset 0x8 - 0xb */
|
||||
CARD32 class_revision;
|
||||
struct {
|
||||
#if X_BYTE_ORDER == X_BIG_ENDIAN
|
||||
CARD8 base_class;
|
||||
CARD8 sub_class;
|
||||
CARD8 prog_if;
|
||||
CARD8 rev_id;
|
||||
#else
|
||||
CARD8 rev_id;
|
||||
CARD8 prog_if;
|
||||
CARD8 sub_class;
|
||||
CARD8 base_class;
|
||||
#endif
|
||||
} cr;
|
||||
} class_rev;
|
||||
|
||||
union { /* Offset 0xc - 0xf */
|
||||
CARD32 bist_header_latency_cache;
|
||||
struct {
|
||||
#if X_BYTE_ORDER == X_BIG_ENDIAN
|
||||
CARD8 bist;
|
||||
CARD8 header_type;
|
||||
CARD8 latency_timer;
|
||||
CARD8 cache_line_size;
|
||||
#else
|
||||
CARD8 cache_line_size;
|
||||
CARD8 latency_timer;
|
||||
CARD8 header_type;
|
||||
CARD8 bist;
|
||||
#endif
|
||||
} bhlc;
|
||||
} bhlc;
|
||||
union { /* Offset 0x10 - 0x3b */
|
||||
struct { /* header type 2 */
|
||||
CARD32 cg_rsrvd1; /* 0x10 */
|
||||
#if X_BYTE_ORDER == X_BIG_ENDIAN
|
||||
CARD16 secondary_status; /* 0x16 */
|
||||
CARD16 cg_rsrvd2; /* 0x14 */
|
||||
|
||||
union {
|
||||
CARD32 cg_bus_reg;
|
||||
struct {
|
||||
CARD8 latency_timer; /* 0x1b */
|
||||
CARD8 subordinate_bus_number; /* 0x1a */
|
||||
CARD8 cardbus_bus_number; /* 0x19 */
|
||||
CARD8 primary_bus_number; /* 0x18 */
|
||||
} cgbr;
|
||||
} cgbr;
|
||||
#else
|
||||
CARD16 cg_rsrvd2; /* 0x14 */
|
||||
CARD16 secondary_status; /* 0x16 */
|
||||
|
||||
union {
|
||||
CARD32 cg_bus_reg;
|
||||
struct {
|
||||
CARD8 primary_bus_number; /* 0x18 */
|
||||
CARD8 cardbus_bus_number; /* 0x19 */
|
||||
CARD8 subordinate_bus_number; /* 0x1a */
|
||||
CARD8 latency_timer; /* 0x1b */
|
||||
} cgbr;
|
||||
} cgbr;
|
||||
#endif
|
||||
CARD32 mem_base0; /* 0x1c */
|
||||
CARD32 mem_limit0; /* 0x20 */
|
||||
CARD32 mem_base1; /* 0x24 */
|
||||
CARD32 mem_limit1; /* 0x28 */
|
||||
CARD32 io_base0; /* 0x2c */
|
||||
CARD32 io_limit0; /* 0x30 */
|
||||
CARD32 io_base1; /* 0x34 */
|
||||
CARD32 io_limit1; /* 0x38 */
|
||||
} cg;
|
||||
struct {
|
||||
union { /* Offset 0x10 - 0x27 */
|
||||
struct { /* header type 0 */
|
||||
CARD32 dv_base0;
|
||||
CARD32 dv_base1;
|
||||
CARD32 dv_base2;
|
||||
CARD32 dv_base3;
|
||||
CARD32 dv_base4;
|
||||
CARD32 dv_base5;
|
||||
} dv;
|
||||
struct { /* header type 1 */
|
||||
CARD32 bg_rsrvd[2];
|
||||
#if X_BYTE_ORDER == X_BIG_ENDIAN
|
||||
union {
|
||||
CARD32 pp_bus_reg;
|
||||
struct {
|
||||
CARD8 secondary_latency_timer;
|
||||
CARD8 subordinate_bus_number;
|
||||
CARD8 secondary_bus_number;
|
||||
CARD8 primary_bus_number;
|
||||
} ppbr;
|
||||
} ppbr;
|
||||
|
||||
CARD16 secondary_status;
|
||||
CARD8 io_limit;
|
||||
CARD8 io_base;
|
||||
|
||||
CARD16 mem_limit;
|
||||
CARD16 mem_base;
|
||||
|
||||
CARD16 prefetch_mem_limit;
|
||||
CARD16 prefetch_mem_base;
|
||||
#else
|
||||
union {
|
||||
CARD32 pp_bus_reg;
|
||||
struct {
|
||||
CARD8 primary_bus_number;
|
||||
CARD8 secondary_bus_number;
|
||||
CARD8 subordinate_bus_number;
|
||||
CARD8 secondary_latency_timer;
|
||||
} ppbr;
|
||||
} ppbr;
|
||||
|
||||
CARD8 io_base;
|
||||
CARD8 io_limit;
|
||||
CARD16 secondary_status;
|
||||
|
||||
CARD16 mem_base;
|
||||
CARD16 mem_limit;
|
||||
|
||||
CARD16 prefetch_mem_base;
|
||||
CARD16 prefetch_mem_limit;
|
||||
#endif
|
||||
} bg;
|
||||
} bc;
|
||||
union { /* Offset 0x28 - 0x2b */
|
||||
CARD32 rsvd1;
|
||||
CARD32 pftch_umem_base;
|
||||
CARD32 cardbus_cis_ptr;
|
||||
} um_c_cis;
|
||||
union { /* Offset 0x2c - 0x2f */
|
||||
CARD32 subsys_card_vendor;
|
||||
CARD32 pftch_umem_limit;
|
||||
CARD32 rsvd2;
|
||||
struct {
|
||||
#if X_BYTE_ORDER == X_BIG_ENDIAN
|
||||
CARD16 subsys_card;
|
||||
CARD16 subsys_vendor;
|
||||
#else
|
||||
CARD16 subsys_vendor;
|
||||
CARD16 subsys_card;
|
||||
#endif
|
||||
} ssys;
|
||||
} um_ssys_id;
|
||||
union { /* Offset 0x30 - 0x33 */
|
||||
CARD32 baserom;
|
||||
struct {
|
||||
#if X_BYTE_ORDER == X_BIG_ENDIAN
|
||||
CARD16 io_ulimit;
|
||||
CARD16 io_ubase;
|
||||
#else
|
||||
CARD16 io_ubase;
|
||||
CARD16 io_ulimit;
|
||||
#endif
|
||||
} b_u_io;
|
||||
} uio_rom;
|
||||
struct {
|
||||
CARD32 rsvd3; /* Offset 0x34 - 0x37 */
|
||||
CARD32 rsvd4; /* Offset 0x38 - 0x3b */
|
||||
} rsvd;
|
||||
} cd;
|
||||
} cx;
|
||||
union { /* Offset 0x3c - 0x3f */
|
||||
union { /* header type 0 */
|
||||
CARD32 max_min_ipin_iline;
|
||||
struct {
|
||||
#if X_BYTE_ORDER == X_BIG_ENDIAN
|
||||
CARD8 max_lat;
|
||||
CARD8 min_gnt;
|
||||
CARD8 int_pin;
|
||||
CARD8 int_line;
|
||||
#else
|
||||
CARD8 int_line;
|
||||
CARD8 int_pin;
|
||||
CARD8 min_gnt;
|
||||
CARD8 max_lat;
|
||||
#endif
|
||||
} mmii;
|
||||
} mmii;
|
||||
struct { /* header type 1 */
|
||||
#if X_BYTE_ORDER == X_BIG_ENDIAN
|
||||
CARD16 bridge_control; /* upper 8 bits reserved */
|
||||
CARD8 rsvd2;
|
||||
CARD8 rsvd1;
|
||||
#else
|
||||
CARD8 rsvd1;
|
||||
CARD8 rsvd2;
|
||||
CARD16 bridge_control; /* upper 8 bits reserved */
|
||||
#endif
|
||||
} bctrl;
|
||||
} bm;
|
||||
union { /* Offset 0x40 - 0xff */
|
||||
CARD32 dwords[48];
|
||||
CARD8 bytes[192];
|
||||
} devspf;
|
||||
} pciCfgRegs;
|
||||
|
||||
typedef union pci_cfg_spc {
|
||||
pciCfgRegs regs;
|
||||
CARD32 dwords[256/sizeof(CARD32)];
|
||||
CARD8 bytes[256/sizeof(CARD8)];
|
||||
} pciCfgSpc;
|
||||
|
||||
/*
|
||||
* Data structure returned by xf86scanpci including contents of
|
||||
* PCI config space header
|
||||
*/
|
||||
typedef struct {
|
||||
PCITAG tag;
|
||||
int busnum;
|
||||
int devnum;
|
||||
int funcnum;
|
||||
pciCfgSpc cfgspc;
|
||||
struct pci_device * dev;
|
||||
} pciDevice, *pciConfigPtr;
|
||||
|
||||
typedef enum {
|
||||
PCI_MEM,
|
||||
PCI_MEM_SIZE,
|
||||
|
|
@ -670,91 +248,13 @@ typedef enum {
|
|||
PCI_IO_SPARSE_MASK
|
||||
} PciAddrType;
|
||||
|
||||
#define pci_device_vendor cfgspc.regs.dv_id.device_vendor
|
||||
#define pci_vendor cfgspc.regs.dv_id.dv.vendor
|
||||
#define _pci_device cfgspc.regs.dv_id.dv.device
|
||||
#define pci_status_command cfgspc.regs.stat_cmd.status_command
|
||||
#define pci_command cfgspc.regs.stat_cmd.sc.command
|
||||
#define pci_status cfgspc.regs.stat_cmd.sc.status
|
||||
#define pci_class_revision cfgspc.regs.class_rev.class_revision
|
||||
#define pci_rev_id cfgspc.regs.class_rev.cr.rev_id
|
||||
#define pci_prog_if cfgspc.regs.class_rev.cr.prog_if
|
||||
#define pci_sub_class cfgspc.regs.class_rev.cr.sub_class
|
||||
#define pci_base_class cfgspc.regs.class_rev.cr.base_class
|
||||
#define pci_bist_header_latency_cache cfgspc.regs.bhlc.bist_header_latency_cache
|
||||
#define pci_cache_line_size cfgspc.regs.bhlc.bhlc.cache_line_size
|
||||
#define pci_latency_timer cfgspc.regs.bhlc.bhlc.latency_timer
|
||||
#define pci_header_type cfgspc.regs.bhlc.bhlc.header_type
|
||||
#define pci_bist cfgspc.regs.bhlc.bhlc.bist
|
||||
#define pci_cb_secondary_status cfgspc.regs.cx.cg.secondary_status
|
||||
#define pci_cb_bus_register cfgspc.regs.cx.cg.cgbr.cg_bus_reg
|
||||
#define pci_cb_primary_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.primary_bus_number
|
||||
#define pci_cb_cardbus_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.cardbus_bus_number
|
||||
#define pci_cb_subordinate_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.subordinate_bus_number
|
||||
#define pci_cb_latency_timer cfgspc.regs.cx.cg.cgbr.cgbr.latency_timer
|
||||
#define pci_cb_membase0 cfgspc.regs.cx.cg.mem_base0
|
||||
#define pci_cb_memlimit0 cfgspc.regs.cx.cg.mem_limit0
|
||||
#define pci_cb_membase1 cfgspc.regs.cx.cg.mem_base1
|
||||
#define pci_cb_memlimit1 cfgspc.regs.cx.cg.mem_limit1
|
||||
#define pci_cb_iobase0 cfgspc.regs.cx.cg.io_base0
|
||||
#define pci_cb_iolimit0 cfgspc.regs.cx.cg.io_limit0
|
||||
#define pci_cb_iobase1 cfgspc.regs.cx.cg.io_base1
|
||||
#define pci_cb_iolimit1 cfgspc.regs.cx.cg.io_limit1
|
||||
#define pci_base0 cfgspc.regs.cx.cd.bc.dv.dv_base0
|
||||
#define pci_base1 cfgspc.regs.cx.cd.bc.dv.dv_base1
|
||||
#define pci_base2 cfgspc.regs.cx.cd.bc.dv.dv_base2
|
||||
#define pci_base3 cfgspc.regs.cx.cd.bc.dv.dv_base3
|
||||
#define pci_base4 cfgspc.regs.cx.cd.bc.dv.dv_base4
|
||||
#define pci_base5 cfgspc.regs.cx.cd.bc.dv.dv_base5
|
||||
#define pci_cardbus_cis_ptr cfgspc.regs.cx.cd.umem_c_cis.cardbus_cis_ptr
|
||||
#define pci_subsys_card_vendor cfgspc.regs.cx.cd.um_ssys_id.subsys_card_vendor
|
||||
#define pci_subsys_vendor cfgspc.regs.cx.cd.um_ssys_id.ssys.subsys_vendor
|
||||
#define pci_subsys_card cfgspc.regs.cx.cd.um_ssys_id.ssys.subsys_card
|
||||
#define pci_baserom cfgspc.regs.cx.cd.uio_rom.baserom
|
||||
#define pci_pp_bus_register cfgspc.regs.cx.cd.bc.bg.ppbr.pp_bus_reg
|
||||
#define pci_primary_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.primary_bus_number
|
||||
#define pci_secondary_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.secondary_bus_number
|
||||
#define pci_subordinate_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.subordinate_bus_number
|
||||
#define pci_secondary_latency_timer cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.secondary_latency_timer
|
||||
#define pci_io_base cfgspc.regs.cx.cd.bc.bg.io_base
|
||||
#define pci_io_limit cfgspc.regs.cx.cd.bc.bg.io_limit
|
||||
#define pci_secondary_status cfgspc.regs.cx.cd.bc.bg.secondary_status
|
||||
#define pci_mem_base cfgspc.regs.cx.cd.bc.bg.mem_base
|
||||
#define pci_mem_limit cfgspc.regs.cx.cd.bc.bg.mem_limit
|
||||
#define pci_prefetch_mem_base cfgspc.regs.cx.cd.bc.bg.prefetch_mem_base
|
||||
#define pci_prefetch_mem_limit cfgspc.regs.cx.cd.bc.bg.prefetch_mem_limit
|
||||
#define pci_rsvd1 cfgspc.regs.cx.cd.um_c_cis.rsvd1
|
||||
#define pci_rsvd2 cfgspc.regs.cx.cd.um_ssys_id.rsvd2
|
||||
#define pci_prefetch_upper_mem_base cfgspc.regs.cx.cd.um_c_cis.pftch_umem_base
|
||||
#define pci_prefetch_upper_mem_limit cfgspc.regs.cx.cd.um_ssys_id.pftch_umem_limit
|
||||
#define pci_upper_io_base cfgspc.regs.cx.cd.uio_rom.b_u_io.io_ubase
|
||||
#define pci_upper_io_limit cfgspc.regs.cx.cd.uio_rom.b_u_io.io_ulimit
|
||||
#define pci_int_line cfgspc.regs.bm.mmii.mmii.int_line
|
||||
#define pci_int_pin cfgspc.regs.bm.mmii.mmii.int_pin
|
||||
#define pci_min_gnt cfgspc.regs.bm.mmii.mmii.min_gnt
|
||||
#define pci_max_lat cfgspc.regs.bm.mmii.mmii.max_lat
|
||||
#define pci_max_min_ipin_iline cfgspc.regs.bm.mmii.max_min_ipin_iline
|
||||
#define pci_bridge_control cfgspc.regs.bm.bctrl.bridge_control
|
||||
#define pci_user_config cfgspc.regs.devspf.dwords[0]
|
||||
#define pci_user_config_0 cfgspc.regs.devspf.bytes[0]
|
||||
#define pci_user_config_1 cfgspc.regs.devspf.bytes[1]
|
||||
#define pci_user_config_2 cfgspc.regs.devspf.bytes[2]
|
||||
#define pci_user_config_3 cfgspc.regs.devspf.bytes[3]
|
||||
|
||||
typedef enum {
|
||||
PCI_BIOS_PC = 0,
|
||||
PCI_BIOS_OPEN_FIRMWARE,
|
||||
PCI_BIOS_HP_PA_RISC,
|
||||
PCI_BIOS_OTHER
|
||||
} PciBiosType;
|
||||
|
||||
/* Public PCI access functions */
|
||||
ADDRESS pciBusAddrToHostAddr(PCITAG tag, PciAddrType type, ADDRESS addr);
|
||||
ADDRESS pciHostAddrToBusAddr(PCITAG tag, PciAddrType type, ADDRESS addr);
|
||||
PCITAG pciTag(int busnum, int devnum, int funcnum);
|
||||
int pciGetBaseSize(PCITAG tag, int indx, Bool destructive, Bool *min);
|
||||
pciConfigPtr *xf86scanpci(int flags);
|
||||
pciConfigPtr xf86GetPciConfigFromTag(PCITAG Tag);
|
||||
Bool xf86scanpci(void);
|
||||
|
||||
extern int pciNumBuses;
|
||||
|
||||
|
|
@ -766,16 +266,4 @@ IOADDRESS xf86MapLegacyIO(struct pci_device *dev);
|
|||
int xf86ReadDomainMemory(PCITAG Tag, ADDRESS Base, int Len,
|
||||
unsigned char *Buf);
|
||||
|
||||
typedef enum {
|
||||
ROM_BASE_PRESET = -2,
|
||||
ROM_BASE_BIOS,
|
||||
ROM_BASE_MEM0 = 0,
|
||||
ROM_BASE_MEM1,
|
||||
ROM_BASE_MEM2,
|
||||
ROM_BASE_MEM3,
|
||||
ROM_BASE_MEM4,
|
||||
ROM_BASE_MEM5,
|
||||
ROM_BASE_FIND
|
||||
} romBaseSource;
|
||||
|
||||
#endif /* _XF86PCI_H */
|
||||
|
|
|
|||
|
|
@ -167,9 +167,9 @@ xf86GetPciOffsetFromOS(PCITAG tag, int index, unsigned long* bases)
|
|||
unsigned long
|
||||
xf86GetOSOffsetFromPCI(PCITAG tag, int space, unsigned long base)
|
||||
{
|
||||
unsigned int dev, fn;
|
||||
unsigned int ndx;
|
||||
struct pci_dev *device;
|
||||
struct pci_device *dev;
|
||||
|
||||
if (!xf86OSLinuxPCIDevs) {
|
||||
xf86OSLinuxPCIDevs = xf86OSLinuxGetPciDevs();
|
||||
|
|
@ -179,26 +179,31 @@ xf86GetOSOffsetFromPCI(PCITAG tag, int space, unsigned long base)
|
|||
}
|
||||
|
||||
for (device = xf86OSLinuxPCIDevs; device; device = device->next) {
|
||||
dev = device->devfn >> 3;
|
||||
fn = device->devfn & 0x7;
|
||||
if (tag == pciTag(device->bus, dev, fn)) {
|
||||
dev = pci_device_find_by_slot(0, device->bus, (device->devfn >> 3),
|
||||
(device->devfn & 0x7));
|
||||
if (dev != NULL) {
|
||||
/* ok now look through all the BAR values of this device */
|
||||
pciConfigPtr pDev = xf86GetPciConfigFromTag(tag);
|
||||
|
||||
for (ndx=0; ndx<7; ndx++) {
|
||||
unsigned long savePtr, flagMask;
|
||||
if (ndx == 6)
|
||||
savePtr = pDev->pci_baserom;
|
||||
else /* this the ROM bar */
|
||||
savePtr = (&pDev->pci_base0)[ndx];
|
||||
/* Ignore unset base addresses. The kernel may
|
||||
* have reported non-zero size and address even
|
||||
* if they are disabled (e.g. disabled ROM BAR).
|
||||
uint32_t savePtr;
|
||||
uint32_t flagMask;
|
||||
|
||||
/* The ROM BAR isn't with the other BARs.
|
||||
*/
|
||||
const pciaddr_t offset = (ndx == 6)
|
||||
? (4 * 12) : (4 * ndx) + 16;
|
||||
|
||||
pci_device_cfg_read_u32(dev, &savePtr, offset);
|
||||
|
||||
/* Ignore unset base addresses. The kernel may have reported
|
||||
* non-zero size and address even if they are disabled (e.g.,
|
||||
* disabled ROM BAR).
|
||||
*/
|
||||
if (savePtr == 0)
|
||||
continue;
|
||||
|
||||
/* Remove memory attribute bits, different for IO
|
||||
* and memory ranges. */
|
||||
* and memory ranges.
|
||||
*/
|
||||
flagMask = (savePtr & 0x1) ? ~0x3UL : ~0xFUL;
|
||||
savePtr &= flagMask;
|
||||
|
||||
|
|
@ -208,7 +213,7 @@ xf86GetOSOffsetFromPCI(PCITAG tag, int space, unsigned long base)
|
|||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user