Whitespace cleanup.
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6870c08157
commit
26c5a8dfdd
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@ -71,18 +71,18 @@ ATIDRIInitGARTValues(ScreenPtr pScreen)
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int s, l;
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atis->gartOffset = 0;
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/* Initialize the ring buffer data */
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atis->ringStart = atis->gartOffset;
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atis->ringMapSize = atis->ringSize*1024*1024 + DRM_PAGE_SIZE;
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atis->ringReadOffset = atis->ringStart + atis->ringMapSize;
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atis->ringReadMapSize = DRM_PAGE_SIZE;
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/* Reserve space for vertex/indirect buffers */
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atis->bufStart = atis->ringReadOffset + atis->ringReadMapSize;
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atis->bufMapSize = atis->bufSize*1024*1024;
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/* Reserve the rest for GART textures */
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atis->gartTexStart = atis->bufStart + atis->bufMapSize;
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s = (atis->gartSize*1024*1024 - atis->gartTexStart);
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@ -98,9 +98,9 @@ ATIDRIAddAndMap(int fd, drmHandle offset, drmSize size,
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drmAddressPtr address, char *desc)
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{
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char *name;
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name = (type == DRM_AGP) ? "agp" : "pci";
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if (drmAddMap(fd, offset, size, type, flags, handle) < 0) {
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ErrorF("[%s] Could not add %s mapping\n", name, desc);
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return FALSE;
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@ -230,7 +230,7 @@ ATIDRIAgpInit(ScreenPtr pScreen)
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MMIO_OUT32(mmio, R128_REG_PCI_GART_PAGE, 1);
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}
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return TRUE;
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return TRUE;
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}
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static Bool
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@ -254,7 +254,6 @@ ATIDRIPciInit(ScreenPtr pScreen)
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ErrorF("[pci] %d kB allocated with handle 0x%08lx\n",
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atis->gartSize*1024, (long)atis->pciMemHandle);
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if (!ATIDRIAddAndMap(atic->drmFd, atis->ringStart, atis->ringMapSize,
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DRM_SCATTER_GATHER, DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL,
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&atis->ringHandle, (drmAddressPtr)&atis->ring, "ring"))
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@ -392,7 +391,7 @@ ATIDRIBufInit(ScreenPtr pScreen)
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ATIScreenInfo(pScreenPriv);
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ATICardInfo(pScreenPriv);
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int type, size;
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if (atic->is_radeon)
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size = RADEON_BUFFER_SIZE;
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else
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@ -479,7 +478,7 @@ ATIDRIScreenInit(ScreenPtr pScreen)
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DRIInfoPtr pDRIInfo;
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int devSareaSize;
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drmSetVersion sv;
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/* XXX: Disable DRI clients for unsupported depths */
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if (atic->is_radeon) {
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@ -606,8 +605,8 @@ ATIDRIScreenInit(ScreenPtr pScreen)
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}
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/* Add a map for the MMIO registers that will be accessed by any
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* DRI-based clients.
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*/
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* DRI-based clients.
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*/
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atis->registerSize = RADEON_REG_SIZE(atic);
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if (drmAddMap(atic->drmFd, RADEON_REG_BASE(pScreenPriv->screen->card),
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atis->registerSize, DRM_REGISTERS, DRM_READ_ONLY,
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@ -745,7 +744,7 @@ RadeonDRIFinishScreenInit(ScreenPtr pScreen)
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drmHeap.region = RADEON_MEM_REGION_GART;
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drmHeap.start = 0;
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drmHeap.size = atis->gartTexMapSize;
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if (drmCommandWrite(atic->drmFd, DRM_RADEON_INIT_HEAP, &drmHeap,
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sizeof(drmHeap))) {
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ErrorF("[drm] Failed to initialize GART heap manager\n");
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@ -767,7 +766,7 @@ RadeonDRIFinishScreenInit(ScreenPtr pScreen)
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pRADEONDRI->IsPCI = !atis->IsAGP;
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pRADEONDRI->AGPMode = atis->agpMode;
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pRADEONDRI->frontOffset = atis->frontOffset;
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pRADEONDRI->frontPitch = atis->frontPitch;
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pRADEONDRI->backOffset = atis->backOffset;
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@ -777,18 +776,18 @@ RadeonDRIFinishScreenInit(ScreenPtr pScreen)
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pRADEONDRI->textureOffset = atis->textureOffset;
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pRADEONDRI->textureSize = atis->textureSize;
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pRADEONDRI->log2TexGran = atis->log2TexGran;
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pRADEONDRI->registerHandle = atis->registerHandle;
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pRADEONDRI->registerSize = atis->registerSize;
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pRADEONDRI->statusHandle = atis->ringReadPtrHandle;
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pRADEONDRI->statusSize = atis->ringReadMapSize;
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pRADEONDRI->gartTexHandle = atis->gartTexHandle;
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pRADEONDRI->gartTexMapSize = atis->gartTexMapSize;
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pRADEONDRI->log2GARTTexGran = atis->log2GARTTexGran;
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pRADEONDRI->gartTexOffset = atis->gartTexStart;
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pRADEONDRI->sarea_priv_offset = sizeof(XF86DRISAREARec);
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return TRUE;
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