andreacavalli/xserver-multidpi
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Finish converting RB2D_DSTCACHE to RB3D_DSTCACHE. Remove an extra pixel

Browse Source 
cache flush in the idle function. Init an extra reg for r200, and
    annotate the TCL_BYPASS better. Also, clean up some style nits from the
    last commit.
This commit is contained in:
Eric Anholt 2005-01-25 03:37:05 +00:00
parent 3b1f1508b1
commit 33155b4fd3
3 changed files with 53 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
hw/kdrive/ati/ati_dma.c
View File

@ -56,8 +56,8 @@ ATIDebugFifo(ATIScreenInfo *atis)
MMIO_IN32(mmio, RADEON_REG_CP_CSQ_STAT));
ErrorF("RADEON_REG_RBBM_STATUS: 0x%08x\n",
MMIO_IN32(mmio, RADEON_REG_RBBM_STATUS));
ErrorF("RADEON_REG_RB2D_DSTCACHE_CTLSTAT: 0x%08x\n",
MMIO_IN32(mmio, RADEON_REG_RB2D_DSTCACHE_CTLSTAT));
ErrorF("RADEON_REG_RB3D_DSTCACHE_CTLSTAT: 0x%08x\n",
MMIO_IN32(mmio, RADEON_REG_RB3D_DSTCACHE_CTLSTAT));
} else {
ErrorF("R128_REG_PM4_BUFFER_CNTL: 0x%08x\n",
MMIO_IN32(mmio, R128_REG_PM4_BUFFER_CNTL));
@ -121,13 +121,13 @@ ATIFlushPixelCache(ATIScreenInfo *atis)
TIMEOUT_LOCALS;
if (atic->is_radeon) {
temp = MMIO_IN32(mmio, RADEON_REG_RB2D_DSTCACHE_CTLSTAT);
temp |= RADEON_RB2D_DC_FLUSH_ALL;
MMIO_OUT32(mmio, RADEON_REG_RB2D_DSTCACHE_CTLSTAT, temp);
temp = MMIO_IN32(mmio, RADEON_REG_RB3D_DSTCACHE_CTLSTAT);
temp |= RADEON_RB3D_DC_FLUSH_ALL;
MMIO_OUT32(mmio, RADEON_REG_RB3D_DSTCACHE_CTLSTAT, temp);
WHILE_NOT_TIMEOUT(.2) {
if ((MMIO_IN32(mmio, RADEON_REG_RB2D_DSTCACHE_CTLSTAT) &
RADEON_RB2D_DC_BUSY) == 0)
if ((MMIO_IN32(mmio, RADEON_REG_RB3D_DSTCACHE_CTLSTAT) &
RADEON_RB3D_DC_BUSY) == 0)
break;
}
} else {
@ -323,7 +323,6 @@ ATIWaitIdle(ATIScreenInfo *atis)
{
ATICardInfo *atic = atis->atic;
char *mmio = atic->reg_base;
RING_LOCALS;
TIMEOUT_LOCALS;
if (atis->indirectBuffer != NULL)
@ -349,16 +348,6 @@ ATIWaitIdle(ATIScreenInfo *atis)
}
#endif
if (atic->is_radeon && (atis->using_pseudo || atis->using_dma)) {
BEGIN_DMA(4);
OUT_REG(RADEON_REG_RB2D_DSTCACHE_CTLSTAT,
RADEON_RB2D_DC_FLUSH_ALL);
OUT_REG(ATI_REG_WAIT_UNTIL,
RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN |
RADEON_WAIT_3D_IDLECLEAN);
END_DMA();
}
if (!atic->is_radeon && (atis->using_pseudo || atis->using_dma)) {
ATIWaitAvailPrimary(atis, atis->cce_pri_size);

40
hw/kdrive/ati/ati_draw.c
View File

@ -140,7 +140,7 @@ ATIDrawSetup(ScreenPtr pScreen)
OUT_REG(R128_REG_CONSTANT_COLOR_C, 0xff000000);
OUT_REG(R128_REG_WINDOW_XY_OFFSET, 0x00000000);
END_DMA();
} else {
} else if (!atic->is_r300) {
/* Setup for R100/R200 Composite */
BEGIN_DMA(8);
OUT_REG(RADEON_REG_RE_TOP_LEFT, 0);
@ -161,12 +161,15 @@ ATIDrawSetup(ScreenPtr pScreen)
RADEON_VTX_ST1_NONPARAMETRIC |
RADEON_TEX1_W_ROUTING_USE_W0);
OUT_REG(RADEON_REG_RB3D_DSTCACHE_MODE,
RADEON_RB2D_DC_2D_CACHE_AUTOFLUSH|
RADEON_RB2D_DC_3D_CACHE_AUTOFLUSH);
RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH |
RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH);
END_DMA();
} else {
BEGIN_DMA(16);
OUT_REG(R200_REG_SE_VAP_CNTL_STATUS, 0 /*RADEON_TCL_BYPASS*/);
BEGIN_DMA(18);
/* XXX: The 0 below should be RADEON_TCL_BYPASS on
* RS300s.
*/
OUT_REG(R200_REG_SE_VAP_CNTL_STATUS, 0);
OUT_REG(R200_REG_PP_CNTL_X, 0);
OUT_REG(R200_REG_PP_TXMULTI_CTL_0, 0);
OUT_REG(R200_REG_SE_VTX_STATE_CNTL, 0);
@ -179,6 +182,11 @@ ATIDrawSetup(ScreenPtr pScreen)
R200_VAP_FORCE_W_TO_ONE |
R200_VAP_VF_MAX_VTX_NUM);
OUT_REG(R200_REG_RE_AUX_SCISSOR_CNTL, 0);
OUT_REG(RADEON_REG_RB3D_DSTCACHE_MODE,
RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH |
RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH |
R200_RB3D_DC_2D_CACHE_AUTOFREE |
R200_RB3D_DC_3D_CACHE_AUTOFREE);
END_DMA();
}
}
@ -191,8 +199,7 @@ RadeonSwitchTo2D(ATIScreenInfo *atis)
ENTER_DRAW(0);
BEGIN_DMA(4);
OUT_REG(RADEON_REG_RB2D_DSTCACHE_CTLSTAT,
RADEON_RB2D_DC_FLUSH);
OUT_REG(RADEON_REG_RB3D_DSTCACHE_CTLSTAT, RADEON_RB3D_DC_FLUSH);
OUT_REG(ATI_REG_WAIT_UNTIL,
RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
END_DMA();
@ -206,8 +213,7 @@ RadeonSwitchTo3D(ATIScreenInfo *atis)
ENTER_DRAW(0);
BEGIN_DMA(4);
OUT_REG(RADEON_REG_RB2D_DSTCACHE_CTLSTAT,
RADEON_RB2D_DC_FLUSH);
OUT_REG(RADEON_REG_RB3D_DSTCACHE_CTLSTAT, RADEON_RB3D_DC_FLUSH);
OUT_REG(ATI_REG_WAIT_UNTIL,
RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN);
END_DMA();
@ -600,8 +606,7 @@ ATIUploadToScreen(PixmapPtr pDst, char *src, int src_pitch)
*/
if (atic->is_radeon) {
BEGIN_DMA(4);
OUT_REG(RADEON_REG_RB2D_DSTCACHE_CTLSTAT,
RADEON_RB2D_DC_FLUSH_ALL);
OUT_REG(RADEON_REG_RB3D_DSTCACHE_CTLSTAT, RADEON_RB3D_DC_FLUSH);
OUT_REG(ATI_REG_WAIT_UNTIL,
RADEON_WAIT_2D_IDLECLEAN |
RADEON_WAIT_3D_IDLECLEAN |
@ -641,8 +646,8 @@ ATIUploadToScreen(PixmapPtr pDst, char *src, int src_pitch)
if (atic->is_radeon) {
BEGIN_DMA(4);
OUT_REG(RADEON_REG_RB2D_DSTCACHE_CTLSTAT,
RADEON_RB2D_DC_FLUSH_ALL);
OUT_REG(RADEON_REG_RB3D_DSTCACHE_CTLSTAT,
RADEON_RB3D_DC_FLUSH_ALL);
OUT_REG(ATI_REG_WAIT_UNTIL,
RADEON_WAIT_2D_IDLECLEAN |
RADEON_WAIT_HOST_IDLECLEAN);
@ -716,9 +721,10 @@ ATIUploadToScratch(PixmapPtr pSrc, PixmapPtr pDst)
/* Flush the pixel cache */
if (atic->is_radeon) {
BEGIN_DMA(2);
OUT_REG(RADEON_REG_RB2D_DSTCACHE_CTLSTAT,
RADEON_RB2D_DC_FLUSH_ALL);
BEGIN_DMA(4);
OUT_REG(RADEON_REG_RB3D_DSTCACHE_CTLSTAT,
RADEON_RB3D_DC_FLUSH_ALL);
OUT_REG(ATI_REG_WAIT_UNTIL, RADEON_WAIT_HOST_IDLECLEAN);
END_DMA();
} else {
BEGIN_DMA(2);
@ -830,7 +836,6 @@ ATIDrawEnable(ScreenPtr pScreen)
atis->kaa.UploadToScreen = NULL;
atis->kaa.UploadToScratch = NULL;
#if 1
/* We can't dispatch 3d commands in PIO mode. */
if (!atis->using_pio) {
if (!atic->is_radeon) {
@ -876,7 +881,6 @@ ATIDrawEnable(ScreenPtr pScreen)
atis->scratch_next = atis->scratch_area->offset;
atis->kaa.UploadToScratch = ATIUploadToScratch;
}
#endif
KdMarkSync(pScreen);
}

45
hw/kdrive/ati/ati_reg.h
View File

@ -1716,29 +1716,32 @@
# define R200_TXA_REPL_ARG_C_MASK (3 << 30)
#define RADEON_REG_RB2D_DSTCACHE_MODE 0x3428
#define RADEON_REG_RB3D_DSTCACHE_MODE 0x3258
# define RADEON_RB2D_DC_CACHE_ENABLE 0
# define RADEON_RB2D_DC_2D_CACHE_DISABLE 1
# define RADEON_RB2D_DC_3D_CACHE_DISABLE 1
# define RADEON_RB2D_DC_CACHE_DISABLE 3
# define RADEON_RB2D_DC_2D_CACHE_LINESIZE_128 4
# define RADEON_RB2D_DC_3D_CACHE_LINESIZE_128 8
# define RADEON_RB2D_DC_2D_CACHE_AUTOFLUSH 0x100
# define RADEON_RB2D_DC_3D_CACHE_AUTOFLUSH 0x200
# define RADEON_RB2D_DC_FORCE_RMW 0x10000
# define RADEON_RB2D_DC_DISABLE_RI_FILL 0x1000000
# define RADEON_RB2D_DC_DISABLE_RI_READ 0x2000000
/* This is a read-only mirror of RADEON_REG_RB3D_DSTCACHE_MODE */
#define RADEON_REG_RB2D_DSTCACHE_CTLSTAT 0x342C
/* This is a read-only mirror of RADEON_REG_RB3D_DSTCACHE_CTLSTAT */
#define RADEON_REG_RB3D_DSTCACHE_MODE 0x3258
# define RADEON_RB3D_DC_CACHE_ENABLE (0)
# define RADEON_RB3D_DC_2D_CACHE_DISABLE (1)
# define RADEON_RB3D_DC_3D_CACHE_DISABLE (2)
# define RADEON_RB3D_DC_CACHE_DISABLE (3)
# define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2)
# define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2)
# define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8)
# define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8)
# define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10)
# define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10)
# define RADEON_RB3D_DC_FORCE_RMW (1 << 16)
# define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24)
# define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25)
# define RADEON_RB3D_DC_DISABLE_MASK_CHK (1 << 26)
/* XXX The 2D shadow isn't writable on the M6. The right fix is to rename
* all uses, but Eric is doing that
*/
/* #define RADEON_REG_RB2D_DSTCACHE_CTLSTAT 0x342C */
#define RADEON_REG_RB2D_DSTCACHE_CTLSTAT 0x325C
#define RADEON_REG_RB3D_DSTCACHE_CTLSTAT 0x325C
# define RADEON_RB2D_DC_FLUSH (3 << 0)
# define RADEON_RB2D_DC_FREE (3 << 2)
# define RADEON_RB2D_DC_FLUSH_ALL 0xf
# define RADEON_RB2D_DC_BUSY (1 << 31)
# define RADEON_RB3D_DC_FLUSH (3 << 0)
# define RADEON_RB3D_DC_FREE (3 << 2)
# define RADEON_RB3D_DC_FLUSH_ALL 0xf
# define RADEON_RB3D_DC_BUSY (1 << 31)
/* PLL register defines */
#define R128_REG_MCLK_CNTL 0x000f