vgahw: Port to pciaccess IO space routines
Reviewed-by: Jeremy Huddleston <jeremyhu@apple.com> Tested-by: Jeremy Huddleston <jeremyhu@apple.com> Signed-off-by: Adam Jackson <ajax@redhat.com> Reviewed-by: Jamey Sharp <jamey@minilop.net>
This commit is contained in:
Adam Jackson
Jeremy Huddleston
parent
4bd6579188
commit
6d9efdce0d
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@ -163,67 +163,67 @@ static CARD8 defaultDAC[768] =
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static void
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stdWriteCrtc(vgaHWPtr hwp, CARD8 index, CARD8 value)
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{
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outb(hwp->IOBase + hwp->PIOOffset + VGA_CRTC_INDEX_OFFSET, index);
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outb(hwp->IOBase + hwp->PIOOffset + VGA_CRTC_DATA_OFFSET, value);
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pci_io_write8(hwp->io, hwp->IOBase + VGA_CRTC_INDEX_OFFSET, index);
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pci_io_write8(hwp->io, hwp->IOBase + VGA_CRTC_DATA_OFFSET, value);
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}
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static CARD8
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stdReadCrtc(vgaHWPtr hwp, CARD8 index)
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{
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outb(hwp->IOBase + hwp->PIOOffset + VGA_CRTC_INDEX_OFFSET, index);
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return inb(hwp->IOBase + hwp->PIOOffset + VGA_CRTC_DATA_OFFSET);
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pci_io_write8(hwp->io, hwp->IOBase + VGA_CRTC_INDEX_OFFSET, index);
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return pci_io_read8(hwp->io, hwp->IOBase + VGA_CRTC_DATA_OFFSET);
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}
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static void
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stdWriteGr(vgaHWPtr hwp, CARD8 index, CARD8 value)
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{
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outb(hwp->PIOOffset + VGA_GRAPH_INDEX, index);
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outb(hwp->PIOOffset + VGA_GRAPH_DATA, value);
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pci_io_write8(hwp->io, VGA_GRAPH_INDEX, index);
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pci_io_write8(hwp->io, VGA_GRAPH_DATA, value);
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}
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static CARD8
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stdReadGr(vgaHWPtr hwp, CARD8 index)
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{
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outb(hwp->PIOOffset + VGA_GRAPH_INDEX, index);
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return inb(hwp->PIOOffset + VGA_GRAPH_DATA);
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pci_io_write8(hwp->io, VGA_GRAPH_INDEX, index);
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return pci_io_read8(hwp->io, VGA_GRAPH_DATA);
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}
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static void
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stdWriteSeq(vgaHWPtr hwp, CARD8 index, CARD8 value)
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{
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outb(hwp->PIOOffset + VGA_SEQ_INDEX, index);
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outb(hwp->PIOOffset + VGA_SEQ_DATA, value);
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pci_io_write8(hwp->io, VGA_SEQ_INDEX, index);
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pci_io_write8(hwp->io, VGA_SEQ_DATA, value);
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}
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static CARD8
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stdReadSeq(vgaHWPtr hwp, CARD8 index)
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{
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outb(hwp->PIOOffset + VGA_SEQ_INDEX, index);
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return inb(hwp->PIOOffset + VGA_SEQ_DATA);
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pci_io_write8(hwp->io, VGA_SEQ_INDEX, index);
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return pci_io_read8(hwp->io, VGA_SEQ_DATA);
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}
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static CARD8
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stdReadST00(vgaHWPtr hwp)
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{
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return inb(hwp->PIOOffset + VGA_IN_STAT_0);
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return pci_io_read8(hwp->io, VGA_IN_STAT_0);
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}
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static CARD8
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stdReadST01(vgaHWPtr hwp)
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{
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return inb(hwp->IOBase + hwp->PIOOffset + VGA_IN_STAT_1_OFFSET);
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return pci_io_read8(hwp->io, hwp->IOBase + VGA_IN_STAT_1_OFFSET);
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}
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static CARD8
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stdReadFCR(vgaHWPtr hwp)
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{
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return inb(hwp->PIOOffset + VGA_FEATURE_R);
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return pci_io_read8(hwp->io, VGA_FEATURE_R);
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}
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static void
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stdWriteFCR(vgaHWPtr hwp, CARD8 value)
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{
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outb(hwp->IOBase + hwp->PIOOffset + VGA_FEATURE_W_OFFSET,value);
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pci_io_write8(hwp->io, hwp->IOBase + VGA_FEATURE_W_OFFSET,value);
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}
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static void
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@ -234,9 +234,9 @@ stdWriteAttr(vgaHWPtr hwp, CARD8 index, CARD8 value)
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else
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index |= 0x20;
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(void) inb(hwp->IOBase + hwp->PIOOffset + VGA_IN_STAT_1_OFFSET);
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outb(hwp->PIOOffset + VGA_ATTR_INDEX, index);
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outb(hwp->PIOOffset + VGA_ATTR_DATA_W, value);
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(void) pci_io_read8(hwp->io, hwp->IOBase + VGA_IN_STAT_1_OFFSET);
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pci_io_write8(hwp->io, VGA_ATTR_INDEX, index);
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pci_io_write8(hwp->io, VGA_ATTR_DATA_W, value);
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}
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static CARD8
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@ -247,85 +247,85 @@ stdReadAttr(vgaHWPtr hwp, CARD8 index)
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else
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index |= 0x20;
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(void) inb(hwp->IOBase + hwp->PIOOffset + VGA_IN_STAT_1_OFFSET);
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outb(hwp->PIOOffset + VGA_ATTR_INDEX, index);
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return inb(hwp->PIOOffset + VGA_ATTR_DATA_R);
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(void) pci_io_read8(hwp->io, hwp->IOBase + VGA_IN_STAT_1_OFFSET);
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pci_io_write8(hwp->io, VGA_ATTR_INDEX, index);
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return pci_io_read8(hwp->io, VGA_ATTR_DATA_R);
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}
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static void
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stdWriteMiscOut(vgaHWPtr hwp, CARD8 value)
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{
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outb(hwp->PIOOffset + VGA_MISC_OUT_W, value);
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pci_io_write8(hwp->io, VGA_MISC_OUT_W, value);
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}
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static CARD8
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stdReadMiscOut(vgaHWPtr hwp)
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{
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return inb(hwp->PIOOffset + VGA_MISC_OUT_R);
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return pci_io_read8(hwp->io, VGA_MISC_OUT_R);
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}
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static void
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stdEnablePalette(vgaHWPtr hwp)
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{
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(void) inb(hwp->IOBase + hwp->PIOOffset + VGA_IN_STAT_1_OFFSET);
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outb(hwp->PIOOffset + VGA_ATTR_INDEX, 0x00);
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(void) pci_io_read8(hwp->io, hwp->IOBase + VGA_IN_STAT_1_OFFSET);
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pci_io_write8(hwp->io, VGA_ATTR_INDEX, 0x00);
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hwp->paletteEnabled = TRUE;
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}
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static void
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stdDisablePalette(vgaHWPtr hwp)
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{
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(void) inb(hwp->IOBase + hwp->PIOOffset + VGA_IN_STAT_1_OFFSET);
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outb(hwp->PIOOffset + VGA_ATTR_INDEX, 0x20);
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(void) pci_io_read8(hwp->io, hwp->IOBase + VGA_IN_STAT_1_OFFSET);
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pci_io_write8(hwp->io, VGA_ATTR_INDEX, 0x20);
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hwp->paletteEnabled = FALSE;
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}
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static void
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stdWriteDacMask(vgaHWPtr hwp, CARD8 value)
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{
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outb(hwp->PIOOffset + VGA_DAC_MASK, value);
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pci_io_write8(hwp->io, VGA_DAC_MASK, value);
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}
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static CARD8
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stdReadDacMask(vgaHWPtr hwp)
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{
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return inb(hwp->PIOOffset + VGA_DAC_MASK);
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return pci_io_read8(hwp->io, VGA_DAC_MASK);
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}
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static void
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stdWriteDacReadAddr(vgaHWPtr hwp, CARD8 value)
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{
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outb(hwp->PIOOffset + VGA_DAC_READ_ADDR, value);
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pci_io_write8(hwp->io, VGA_DAC_READ_ADDR, value);
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}
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static void
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stdWriteDacWriteAddr(vgaHWPtr hwp, CARD8 value)
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{
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outb(hwp->PIOOffset + VGA_DAC_WRITE_ADDR, value);
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pci_io_write8(hwp->io, VGA_DAC_WRITE_ADDR, value);
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}
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static void
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stdWriteDacData(vgaHWPtr hwp, CARD8 value)
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{
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outb(hwp->PIOOffset + VGA_DAC_DATA, value);
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pci_io_write8(hwp->io, VGA_DAC_DATA, value);
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}
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static CARD8
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stdReadDacData(vgaHWPtr hwp)
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{
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return inb(hwp->PIOOffset + VGA_DAC_DATA);
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return pci_io_read8(hwp->io, VGA_DAC_DATA);
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}
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static CARD8
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stdReadEnable(vgaHWPtr hwp)
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{
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return inb(hwp->PIOOffset + VGA_ENABLE);
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return pci_io_read8(hwp->io, VGA_ENABLE);
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}
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static void
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stdWriteEnable(vgaHWPtr hwp, CARD8 value)
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{
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outb(hwp->PIOOffset + VGA_ENABLE, value);
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pci_io_write8(hwp->io, VGA_ENABLE, value);
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}
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void
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@ -353,9 +353,10 @@ vgaHWSetStdFuncs(vgaHWPtr hwp)
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hwp->writeDacReadAddr = stdWriteDacReadAddr;
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hwp->writeDacData = stdWriteDacData;
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hwp->readDacData = stdReadDacData;
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hwp->PIOOffset = 0;
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hwp->readEnable = stdReadEnable;
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hwp->writeEnable = stdWriteEnable;
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hwp->io = pci_legacy_open_io(hwp->dev, 0, 64 * 1024);
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}
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/*
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@ -1719,7 +1720,9 @@ vgaHWFreeHWRec(ScrnInfoPtr scrp)
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vgaHWPtr hwp = VGAHWPTR(scrp);
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if (!hwp)
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return;
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return;
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pci_device_close_io(hwp->dev, hwp->io);
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free(hwp->FontInfo1);
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free(hwp->FontInfo2);
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@ -1789,8 +1792,7 @@ vgaHWGetIOBase(vgaHWPtr hwp)
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hwp->IOBase = (hwp->readMiscOut(hwp) & 0x01) ?
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VGA_IOBASE_COLOR : VGA_IOBASE_MONO;
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xf86DrvMsgVerb(hwp->pScrn->scrnIndex, X_INFO, 3,
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"vgaHWGetIOBase: hwp->IOBase is 0x%04x, hwp->PIOOffset is 0x%04lx\n",
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hwp->IOBase, hwp->PIOOffset);
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"vgaHWGetIOBase: hwp->IOBase is 0x%04x\n", hwp->IOBase);
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}
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@ -1995,11 +1997,12 @@ SaveScreenProcPtr vgaHWSaveScreenWeak(void)
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void
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xf86GetClocks(ScrnInfoPtr pScrn, int num, Bool (*ClockFunc)(ScrnInfoPtr, int),
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void (*ProtectRegs)(ScrnInfoPtr, Bool),
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void (*BlankScreen)(ScrnInfoPtr, Bool), IOADDRESS vertsyncreg,
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void (*BlankScreen)(ScrnInfoPtr, Bool), unsigned long vertsyncreg,
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int maskval, int knownclkindex, int knownclkvalue)
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{
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register int status = vertsyncreg;
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unsigned long i, cnt, rcnt, sync;
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vgaHWPtr hwp = VGAHWPTR(pScrn);
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/* First save registers that get written on */
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(*ClockFunc)(pScrn, CLK_REG_SAVE);
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@ -2026,22 +2029,22 @@ xf86GetClocks(ScrnInfoPtr pScrn, int num, Bool (*ClockFunc)(ScrnInfoPtr, int),
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cnt = 0;
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sync = 200000;
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while ((inb(status) & maskval) == 0x00)
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while ((pci_io_read8(hwp->io, status) & maskval) == 0x00)
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if (sync-- == 0) goto finish;
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/* Something appears to be happening, so reset sync count */
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sync = 200000;
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while ((inb(status) & maskval) == maskval)
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while ((pci_io_read8(hwp->io, status) & maskval) == maskval)
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if (sync-- == 0) goto finish;
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/* Something appears to be happening, so reset sync count */
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sync = 200000;
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while ((inb(status) & maskval) == 0x00)
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while ((pci_io_read8(hwp->io, status) & maskval) == 0x00)
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if (sync-- == 0) goto finish;
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for (rcnt = 0; rcnt < 5; rcnt++)
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{
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while (!(inb(status) & maskval))
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while (!(pci_io_read8(hwp->io, status) & maskval))
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cnt++;
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while ((inb(status) & maskval))
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while ((pci_io_read8(hwp->io, status) & maskval))
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cnt++;
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}
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@ -151,17 +151,13 @@ typedef struct _vgaHWRec {
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vgaHWWriteProcPtr writeDacData;
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vgaHWReadProcPtr readDacData;
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pointer ddc;
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IOADDRESS PIOOffset; /* offset + vgareg
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= pioreg */
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struct pci_io_handle *io;
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vgaHWReadProcPtr readEnable;
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vgaHWWriteProcPtr writeEnable;
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struct pci_device *dev;
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} vgaHWRec;
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/* Some macros that VGA drivers can use in their ChipProbe() function */
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#define VGAHW_GET_IOBASE() ((inb(VGA_MISC_OUT_R) & 0x01) ? \
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VGA_IOBASE_COLOR : VGA_IOBASE_MONO)
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#define OVERSCAN 0x11 /* Index of OverScan register */
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/* Flags that define how overscan correction should take place */
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@ -174,15 +170,11 @@ typedef struct _vgaHWRec {
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#define BITS_PER_GUN 6
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#define COLORMAP_SIZE 256
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#if defined(__powerpc__) || defined(__arm__) || defined(__s390__) || defined(__nds32__)
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#define DACDelay(hw) /* No legacy VGA support */
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#else
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#define DACDelay(hw) \
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do { \
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(void)inb((hw)->PIOOffset + (hw)->IOBase + VGA_IN_STAT_1_OFFSET); \
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(void)inb((hw)->PIOOffset + (hw)->IOBase + VGA_IN_STAT_1_OFFSET); \
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#define DACDelay(hw) \
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do { \
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pci_io_read8((hw)->io, (hw)->IOBase + VGA_IN_STAT_1_OFFSET); \
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pci_io_read8((hw)->io, (hw)->IOBase + VGA_IN_STAT_1_OFFSET); \
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} while (0)
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#endif
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/* Function Prototypes */
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@ -235,7 +227,7 @@ extern _X_EXPORT void xf86GetClocks(ScrnInfoPtr pScrn, int num,
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Bool (*ClockFunc)(ScrnInfoPtr, int),
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void (*ProtectRegs)(ScrnInfoPtr, Bool),
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void (*BlankScreen)(ScrnInfoPtr, Bool),
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IOADDRESS vertsyncreg, int maskval,
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unsigned long vertsyncreg, int maskval,
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int knownclkindex, int knownclkvalue);
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#endif /* _VGAHW_H */
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