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Fix the R200 Render code. Composite and Trapezoids are now supported just

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as well as on R100.
This commit is contained in:
Eric Anholt 2004-09-20 03:12:00 +00:00
parent 908287adda
commit b600fcda38
3 changed files with 45 additions and 22 deletions
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17
hw/kdrive/ati/ati_draw.c
View File

@ -162,14 +162,15 @@ ATIDrawSetup(ScreenPtr pScreen)
RADEON_TEX1_W_ROUTING_USE_W0);
END_DMA();
} else {
BEGIN_DMA(12);
BEGIN_DMA(8);
OUT_REG(R200_REG_RE_CNTL, 0);
OUT_REG(R200_REG_SE_VTE_CNTL, R200_VTX_XY_FMT);
OUT_REG(R200_REG_SE_VTX_FMT_0, R200_VTX_XY);
OUT_REG(R200_REG_SE_VTX_FMT_1,
(2 << R200_VTX_TEX0_COMP_CNT_SHIFT) |
(2 << R200_VTX_TEX1_COMP_CNT_SHIFT));
OUT_REG(R200_REG_SE_VAP_CNTL, 0);
/* XXX: VTX_ST_DENORMALIZED is illegal for the case of
* repeating textures.
*/
OUT_REG(R200_REG_SE_VTE_CNTL, R200_VTX_ST_DENORMALIZED);
OUT_REG(R200_REG_SE_VAP_CNTL,
R200_VAP_FORCE_W_TO_ONE |
R200_VAP_VF_MAX_VTX_NUM);
OUT_REG(R200_REG_RE_AUX_SCISSOR_CNTL, 0);
END_DMA();
}
@ -789,7 +790,7 @@ ATIDrawEnable(ScreenPtr pScreen)
/*atis->kaa.PrepareTrapezoids = R128PrepareTrapezoids;
atis->kaa.Trapezoids = R128Trapezoids;
atis->kaa.DoneTrapezoids = R128DoneTrapezoids;*/
} else if (atic->is_r100) {
} else if (atic->is_r100 || atic->is_r200) {
atis->kaa.PrepareTrapezoids = RadeonPrepareTrapezoids;
atis->kaa.Trapezoids = RadeonTrapezoids;
atis->kaa.DoneTrapezoids = RadeonDoneTrapezoids;

1
hw/kdrive/ati/ati_reg.h
View File

@ -1180,6 +1180,7 @@
# define R200_VAP_FORCE_W_TO_ONE 0x00010000
# define R200_VAP_D3D_TEX_DEFAULT 0x00020000
# define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18
# define R200_VAP_VF_MAX_VTX_NUM (9 << 18)
# define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000
#define R200_REG_SE_VTX_FMT_0 0x2088

49
hw/kdrive/ati/radeon_composite.c
View File

@ -511,7 +511,7 @@ R200PrepareComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
is_transform[1] = FALSE;
}
BEGIN_DMA(34);
BEGIN_DMA(22);
OUT_REG(ATI_REG_WAIT_UNTIL,
RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN);
@ -524,6 +524,11 @@ R200PrepareComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
OUT_RING(dst_format | RADEON_ALPHA_BLEND_ENABLE);
OUT_RING(dst_offset);
OUT_REG(R200_REG_SE_VTX_FMT_0, R200_VTX_XY);
OUT_REG(R200_REG_SE_VTX_FMT_1,
(2 << R200_VTX_TEX0_COMP_CNT_SHIFT) |
(2 << R200_VTX_TEX1_COMP_CNT_SHIFT));
OUT_REG(RADEON_REG_RB3D_COLORPITCH, dst_pitch >> pixel_shift);
/* IN operator: Multiply src by mask components or mask alpha.
@ -685,6 +690,7 @@ RadeonPrepareTrapezoids(PicturePtr pDstPicture, PixmapPtr pDst)
{
KdScreenPriv(pDst->drawable.pScreen);
ATIScreenInfo(pScreenPriv);
ATICardInfo(pScreenPriv);
CARD32 dst_offset, dst_pitch;
int pixel_shift;
RING_LOCALS;
@ -701,7 +707,7 @@ RadeonPrepareTrapezoids(PicturePtr pDstPicture, PixmapPtr pDst)
if (((dst_pitch >> pixel_shift) & 0x7) != 0)
ATI_FALLBACK(("Bad destination pitch 0x%x\n", dst_pitch));
BEGIN_DMA(14);
BEGIN_DMA(10);
OUT_REG(ATI_REG_WAIT_UNTIL,
RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN);
@ -718,21 +724,36 @@ RadeonPrepareTrapezoids(PicturePtr pDstPicture, PixmapPtr pDst)
OUT_RING(((pDst->drawable.height - 1) << 16) |
(pDst->drawable.width - 1));
OUT_RING(dst_pitch >> pixel_shift);
/* RADEON_REG_PP_TXCBLEND_0,
* RADEON_REG_PP_TXABLEND_0,
* RADEON_REG_PP_TFACTOR_0
*/
OUT_RING(DMA_PACKET0(RADEON_REG_PP_TXCBLEND_0, 3));
OUT_RING(RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX |
RADEON_COLOR_ARG_C_TFACTOR_ALPHA);
OUT_RING(RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX |
RADEON_ALPHA_ARG_C_TFACTOR_ALPHA);
OUT_RING(0x01000000);
OUT_REG(RADEON_REG_RB3D_BLENDCNTL, RadeonBlendOp[PictOpAdd].blend_cntl);
END_DMA();
if (atic->is_r100) {
BEGIN_DMA(4);
/* RADEON_REG_PP_TXCBLEND_0,
* RADEON_REG_PP_TXABLEND_0,
* RADEON_REG_PP_TFACTOR_0
*/
OUT_RING(DMA_PACKET0(RADEON_REG_PP_TXCBLEND_0, 3));
OUT_RING(RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX |
RADEON_COLOR_ARG_C_TFACTOR_ALPHA);
OUT_RING(RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX |
RADEON_ALPHA_ARG_C_TFACTOR_ALPHA);
OUT_RING(0x01000000);
END_DMA();
} else if (atic->is_r200) {
BEGIN_DMA(12);
OUT_REG(R200_REG_SE_VTX_FMT_0, R200_VTX_XY);
OUT_REG(R200_REG_SE_VTX_FMT_1, 0);
OUT_REG(R200_REG_PP_TXCBLEND_0,
R200_TXC_ARG_C_TFACTOR_COLOR);
OUT_REG(R200_REG_PP_TXABLEND_0,
R200_TXA_ARG_C_TFACTOR_ALPHA);
OUT_REG(R200_REG_PP_TXCBLEND2_0, 0);
OUT_REG(R200_REG_PP_TXABLEND2_0, 0);
OUT_REG(RADEON_REG_PP_TFACTOR_0, 0x01000000);
END_DMA();
}
return TRUE;
}