- Add new Composite hook for kdrive drivers, which only ensures that the
pixmaps are offscreen and don't have alpha maps. It is the last case
checked before going to software fallback
- Use the new Composite hook in the ati driver to implement acceleration of
most Composites that get done in an xcompmgr environment on r100 series
cards. It is only available when using the DRM. There are still some
corruption issues, but the DRI is still non-default and I need to get
this into version control.
This commit is contained in:
Eric Anholt
parent
adfc1ed8e1
commit
c8eb20a08e
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@ -9,6 +9,7 @@ DRI_SOURCES = ati_dri.c \
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r128_common.h \
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r128_sarea.h \
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radeon_common.h \
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radeon_composite.c \
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radeon_sarea.h
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endif
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@ -213,7 +213,7 @@ R128WaitIdle(void)
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}
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}
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static void
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void
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ATIWaitIdle(void)
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{
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ATIScreenInfo *atis = accel_atis;
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@ -349,6 +349,35 @@ drmBufPtr ATIDMAGetBuffer()
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buf->used = 0;
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return buf;
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}
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/* The hardware has a cache on the memory controller for writes to the
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* destination, which I guess is separate for 2d and 3d. So, when switching
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* between 2d and 3d you need to wait for idle and for the cache to clean.
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*/
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void
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RadeonSwitchTo2D(void)
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{
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ATIScreenInfo *atis = accel_atis;
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RING_LOCALS;
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BEGIN_RING(2);
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OUT_RING(DMA_PACKET0(RADEON_REG_WAIT_UNTIL, 0));
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OUT_RING(RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
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ADVANCE_RING();
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}
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void
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RadeonSwitchTo3D(void)
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{
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ATIScreenInfo *atis = accel_atis;
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RING_LOCALS;
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BEGIN_RING(2);
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OUT_RING(DMA_PACKET0(RADEON_REG_WAIT_UNTIL, 0));
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OUT_RING(RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN);
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ADVANCE_RING();
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}
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#endif /* USE_DRI */
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static Bool
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@ -445,6 +474,13 @@ ATIDrawInit(ScreenPtr pScreen)
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atis->kaa.PrepareBlend = R128PrepareBlendDMA;
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atis->kaa.Blend = R128BlendDMA;
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atis->kaa.DoneBlend = R128DoneBlendDMA;
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} else if (!atic->is_r200) {
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atis->kaa.PrepareBlend = RadeonPrepareBlend;
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atis->kaa.Blend = RadeonBlend;
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atis->kaa.DoneBlend = RadeonDoneBlend;
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atis->kaa.PrepareComposite = RadeonPrepareComposite;
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atis->kaa.Composite = RadeonComposite;
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atis->kaa.DoneComposite = RadeonDoneComposite;
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}
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} else {
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#else
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@ -67,8 +67,23 @@ void ATIDMADispatchIndirect(Bool discard);
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void ATIDMAStart(ScreenPtr pScreen);
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void ATIDMAStop(ScreenPtr pScreen);
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Bool RadeonPrepareBlend(int op, PicturePtr pSrcPicture, PicturePtr pDstPicture,
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PixmapPtr pSrc, PixmapPtr pDst);
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void RadeonBlend(int srcX, int srcY, int dstX, int dstY, int width, int height);
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Bool RadeonPrepareComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
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PicturePtr pDstPicture, PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst);
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void RadeonDoneBlend(void);
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void RadeonComposite(int srcX, int srcY, int maskX, int maskY, int dstX,
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int dstY, int w, int h);
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void RadeonDoneComposite(void);
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void RadeonSwitchTo2D(void);
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void RadeonSwitchTo3D(void);
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#endif /* USE_DRI */
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void
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ATIWaitIdle(void);
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#if 0
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#define ATI_FALLBACK(x) \
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do { \
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@ -69,6 +69,10 @@ TAG(ATISetup)(PixmapPtr pDst, PixmapPtr pSrc)
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ATI_FALLBACK(("Bad src offset 0x%x\n", src_offset));
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}
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#ifdef USE_DMA
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if (atic->is_radeon && !atic->is_r200)
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RadeonSwitchTo2D();
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#endif
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BEGIN((pSrc != NULL) ? 3 : 2);
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if (atic->is_radeon) {
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OUT_REG(RADEON_REG_DST_PITCH_OFFSET,
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@ -23,11 +23,14 @@
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*/
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/* $Header$ */
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/* The Radeon register definitions are almost all the same for r128 */
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/* Many of the Radeon register defines are the same for the r128 */
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#define RADEON_REG_BUS_CNTL 0x0030
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# define RADEON_BUS_MASTER_DIS (1 << 6)
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#define RADEON_GEN_INT_CNTL 0x0040
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#define RADEON_REG_AGP_BASE 0x0170
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#define RADEON_REG_AGP_CNTL 0x0174
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# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)
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# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)
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@ -37,16 +40,20 @@
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# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)
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# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)
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# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)
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#define RADEON_REG_RBBM_STATUS 0x0e40
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# define RADEON_RBBM_FIFOCNT_MASK 0x007f
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# define RADEON_RBBM_ACTIVE (1 << 31)
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#define RADEON_REG_CP_CSQ_CNTL 0x0740
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# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
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#define RADEON_REG_SRC_PITCH_OFFSET 0x1428
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#define RADEON_REG_DST_PITCH_OFFSET 0x142c
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#define RADEON_REG_SRC_Y_X 0x1434
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#define RADEON_REG_DST_Y_X 0x1438
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#define RADEON_REG_DST_HEIGHT_WIDTH 0x143c
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#define RADEON_REG_DP_GUI_MASTER_CNTL 0x146c
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# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
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# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
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@ -57,22 +64,462 @@
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# define RADEON_GMC_3D_FCN_EN (1 << 27)
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# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
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# define RADEON_GMC_AUX_CLIP_DIS (1 << 29)
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#define RADEON_REG_DP_BRUSH_FRGD_CLR 0x147c
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#define RADEON_REG_DST_WIDTH_HEIGHT 0x1598
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#define RADEON_REG_CLR_CMP_CNTL 0x15c0
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#define RADEON_REG_AUX_SC_CNTL 0x1660
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#define RADEON_REG_DP_CNTL 0x16c0
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# define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0)
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# define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1)
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#define RADEON_REG_DP_MIX 0x16c8
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#define RADEON_REG_DP_WRITE_MASK 0x16cc
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#define RADEON_REG_DEFAULT_OFFSET 0x16e0
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#define RADEON_REG_DEFAULT_PITCH 0x16e4
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#define RADEON_REG_DEFAULT_SC_BOTTOM_RIGHT 0x16e8
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# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
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# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
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#define RADEON_REG_SC_TOP_LEFT 0x16ec
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#define RADEON_REG_SC_BOTTOM_RIGHT 0x16f0
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#define RADEON_REG_WAIT_UNTIL 0x1720
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# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
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# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
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# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
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# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
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#define RADEON_RB3D_BLENDCNTL 0x1c20
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# define RADEON_COMB_FCN_MASK (3 << 12)
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# define RADEON_COMB_FCN_ADD_CLAMP (0 << 12)
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# define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12)
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# define RADEON_COMB_FCN_SUB_CLAMP (2 << 12)
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# define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12)
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# define RADEON_SRC_BLEND_GL_ZERO (32 << 16)
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# define RADEON_SRC_BLEND_GL_ONE (33 << 16)
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# define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16)
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# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16)
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# define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16)
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# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16)
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# define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16)
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# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16)
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# define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16)
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# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16)
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# define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16)
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# define RADEON_SRC_BLEND_MASK (63 << 16)
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# define RADEON_DST_BLEND_GL_ZERO (32 << 24)
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# define RADEON_DST_BLEND_GL_ONE (33 << 24)
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# define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24)
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# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24)
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# define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24)
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# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24)
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# define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24)
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# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24)
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# define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24)
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# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24)
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# define RADEON_DST_BLEND_MASK (63 << 24)
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#define RADEON_REG_PP_CNTL 0x1c38
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# define RADEON_STIPPLE_ENABLE (1 << 0)
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# define RADEON_SCISSOR_ENABLE (1 << 1)
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# define RADEON_PATTERN_ENABLE (1 << 2)
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# define RADEON_SHADOW_ENABLE (1 << 3)
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# define RADEON_TEX_ENABLE_MASK (0xf << 4)
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# define RADEON_TEX_0_ENABLE (1 << 4)
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# define RADEON_TEX_1_ENABLE (1 << 5)
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# define RADEON_TEX_2_ENABLE (1 << 6)
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# define RADEON_TEX_3_ENABLE (1 << 7)
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# define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12)
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# define RADEON_TEX_BLEND_0_ENABLE (1 << 12)
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# define RADEON_TEX_BLEND_1_ENABLE (1 << 13)
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# define RADEON_TEX_BLEND_2_ENABLE (1 << 14)
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# define RADEON_TEX_BLEND_3_ENABLE (1 << 15)
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# define RADEON_PLANAR_YUV_ENABLE (1 << 20)
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# define RADEON_SPECULAR_ENABLE (1 << 21)
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# define RADEON_FOG_ENABLE (1 << 22)
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# define RADEON_ALPHA_TEST_ENABLE (1 << 23)
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# define RADEON_ANTI_ALIAS_NONE (0 << 24)
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# define RADEON_ANTI_ALIAS_LINE (1 << 24)
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# define RADEON_ANTI_ALIAS_POLY (2 << 24)
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# define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24)
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# define RADEON_BUMP_MAP_ENABLE (1 << 26)
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# define RADEON_BUMPED_MAP_T0 (0 << 27)
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# define RADEON_BUMPED_MAP_T1 (1 << 27)
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# define RADEON_BUMPED_MAP_T2 (2 << 27)
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# define RADEON_TEX_3D_ENABLE_0 (1 << 29)
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# define RADEON_TEX_3D_ENABLE_1 (1 << 30)
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# define RADEON_MC_ENABLE (1 << 31)
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#define RADEON_REG_RB3D_CNTL 0x1c3c
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# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
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# define RADEON_PLANE_MASK_ENABLE (1 << 1)
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# define RADEON_DITHER_ENABLE (1 << 2)
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# define RADEON_ROUND_ENABLE (1 << 3)
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# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
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# define RADEON_DITHER_INIT (1 << 5)
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# define RADEON_ROP_ENABLE (1 << 6)
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# define RADEON_STENCIL_ENABLE (1 << 7)
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# define RADEON_Z_ENABLE (1 << 8)
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# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9)
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# define RADEON_COLOR_FORMAT_ARGB1555 (3 << 10)
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# define RADEON_COLOR_FORMAT_RGB565 (4 << 10)
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# define RADEON_COLOR_FORMAT_ARGB8888 (6 << 10)
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# define RADEON_COLOR_FORMAT_RGB332 (7 << 10)
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# define RADEON_COLOR_FORMAT_Y8 (8 << 10)
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# define RADEON_COLOR_FORMAT_RGB8 (9 << 10)
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# define RADEON_COLOR_FORMAT_YUV422_VYUY (11 << 10)
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# define RADEON_COLOR_FORMAT_YUV422_YVYU (12 << 10)
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# define RADEON_COLOR_FORMAT_aYUV444 (14 << 10)
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# define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10)
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# define RADEON_CLRCMP_FLIP_ENABLE (1 << 14)
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#define RADEON_REG_RB3D_COLOROFFSET 0x1c40
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# define RADEON_COLOROFFSET_MASK 0xfffffff0
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#define RADEON_REG_RE_WIDTH_HEIGHT 0x1c44
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#define RADEON_REG_RB3D_COLORPITCH 0x1c48
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# define RADEON_COLORPITCH_MASK 0x000001ff8
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# define RADEON_COLOR_TILE_ENABLE (1 << 16)
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# define RADEON_COLOR_MICROTILE_ENABLE (1 << 17)
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# define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18)
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# define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18)
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# define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18)
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#define RADEON_REG_SE_CNTL 0x1c4c
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# define RADEON_FFACE_CULL_CW (0 << 0)
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# define RADEON_FFACE_CULL_CCW (1 << 0)
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# define RADEON_FFACE_CULL_DIR_MASK (1 << 0)
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# define RADEON_BFACE_CULL (0 << 1)
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# define RADEON_BFACE_SOLID (3 << 1)
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# define RADEON_FFACE_CULL (0 << 3)
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# define RADEON_FFACE_SOLID (3 << 3)
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# define RADEON_FFACE_CULL_MASK (3 << 3)
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# define RADEON_BADVTX_CULL_DISABLE (1 << 5)
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# define RADEON_FLAT_SHADE_VTX_0 (0 << 6)
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# define RADEON_FLAT_SHADE_VTX_1 (1 << 6)
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# define RADEON_FLAT_SHADE_VTX_2 (2 << 6)
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# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
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# define RADEON_DIFFUSE_SHADE_SOLID (0 << 8)
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# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
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# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
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# define RADEON_DIFFUSE_SHADE_MASK (3 << 8)
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# define RADEON_ALPHA_SHADE_SOLID (0 << 10)
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# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
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# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
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# define RADEON_ALPHA_SHADE_MASK (3 << 10)
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# define RADEON_SPECULAR_SHADE_SOLID (0 << 12)
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# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
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# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
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# define RADEON_SPECULAR_SHADE_MASK (3 << 12)
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# define RADEON_FOG_SHADE_SOLID (0 << 14)
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# define RADEON_FOG_SHADE_FLAT (1 << 14)
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# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
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# define RADEON_FOG_SHADE_MASK (3 << 14)
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# define RADEON_ZBIAS_ENABLE_POINT (1 << 16)
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# define RADEON_ZBIAS_ENABLE_LINE (1 << 17)
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# define RADEON_ZBIAS_ENABLE_TRI (1 << 18)
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# define RADEON_WIDELINE_ENABLE (1 << 20)
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# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
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# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
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# define RADEON_VTX_PIX_CENTER_D3D (0 << 27)
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# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
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# define RADEON_ROUND_MODE_TRUNC (0 << 28)
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# define RADEON_ROUND_MODE_ROUND (1 << 28)
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# define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28)
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# define RADEON_ROUND_MODE_ROUND_ODD (3 << 28)
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# define RADEON_ROUND_PREC_16TH_PIX (0 << 30)
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# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
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# define RADEON_ROUND_PREC_4TH_PIX (2 << 30)
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# define RADEON_ROUND_PREC_HALF_PIX (3 << 30)
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#define RADEON_REG_SE_COORD_FMT 0x1c50
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# define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0)
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# define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1)
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# define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8)
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# define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9)
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# define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10)
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# define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11)
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# define RADEON_VTX_W0_NORMALIZE (1 << 12)
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# define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16)
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# define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17)
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# define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19)
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# define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21)
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# define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23)
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# define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26)
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# define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26)
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|
||||
#define RADEON_REG_PP_TXFILTER_0 0x1c54
|
||||
#define RADEON_REG_PP_TXFILTER_1 0x1c6c
|
||||
#define RADEON_REG_PP_TXFILTER_2 0x1c84
|
||||
# define RADEON_MAG_FILTER_NEAREST (0 << 0)
|
||||
# define RADEON_MAG_FILTER_LINEAR (1 << 0)
|
||||
# define RADEON_MAG_FILTER_MASK (1 << 0)
|
||||
# define RADEON_MIN_FILTER_NEAREST (0 << 1)
|
||||
# define RADEON_MIN_FILTER_LINEAR (1 << 1)
|
||||
# define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)
|
||||
# define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)
|
||||
# define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)
|
||||
# define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)
|
||||
# define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1)
|
||||
# define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1)
|
||||
# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)
|
||||
# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)
|
||||
# define RADEON_MIN_FILTER_MASK (15 << 1)
|
||||
# define RADEON_MAX_ANISO_1_TO_1 (0 << 5)
|
||||
# define RADEON_MAX_ANISO_2_TO_1 (1 << 5)
|
||||
# define RADEON_MAX_ANISO_4_TO_1 (2 << 5)
|
||||
# define RADEON_MAX_ANISO_8_TO_1 (3 << 5)
|
||||
# define RADEON_MAX_ANISO_16_TO_1 (4 << 5)
|
||||
# define RADEON_MAX_ANISO_MASK (7 << 5)
|
||||
# define RADEON_LOD_BIAS_MASK (0xff << 8)
|
||||
# define RADEON_LOD_BIAS_SHIFT 8
|
||||
# define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16)
|
||||
# define RADEON_MAX_MIP_LEVEL_SHIFT 16
|
||||
# define RADEON_YUV_TO_RGB (1 << 20)
|
||||
# define RADEON_YUV_TEMPERATURE_COOL (0 << 21)
|
||||
# define RADEON_YUV_TEMPERATURE_HOT (1 << 21)
|
||||
# define RADEON_YUV_TEMPERATURE_MASK (1 << 21)
|
||||
# define RADEON_WRAPEN_S (1 << 22)
|
||||
# define RADEON_CLAMP_S_WRAP (0 << 23)
|
||||
# define RADEON_CLAMP_S_MIRROR (1 << 23)
|
||||
# define RADEON_CLAMP_S_CLAMP_LAST (2 << 23)
|
||||
# define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)
|
||||
# define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23)
|
||||
# define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)
|
||||
# define RADEON_CLAMP_S_CLAMP_GL (6 << 23)
|
||||
# define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)
|
||||
# define RADEON_CLAMP_S_MASK (7 << 23)
|
||||
# define RADEON_WRAPEN_T (1 << 26)
|
||||
# define RADEON_CLAMP_T_WRAP (0 << 27)
|
||||
# define RADEON_CLAMP_T_MIRROR (1 << 27)
|
||||
# define RADEON_CLAMP_T_CLAMP_LAST (2 << 27)
|
||||
# define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)
|
||||
# define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27)
|
||||
# define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)
|
||||
# define RADEON_CLAMP_T_CLAMP_GL (6 << 27)
|
||||
# define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)
|
||||
# define RADEON_CLAMP_T_MASK (7 << 27)
|
||||
# define RADEON_BORDER_MODE_OGL (0 << 31)
|
||||
# define RADEON_BORDER_MODE_D3D (1 << 31)
|
||||
|
||||
#define RADEON_REG_PP_TXFORMAT_0 0x1c58
|
||||
#define RADEON_REG_PP_TXFORMAT_1 0x1c70
|
||||
#define RADEON_REG_PP_TXFORMAT_2 0x1c88
|
||||
# define RADEON_TXFORMAT_I8 (0 << 0)
|
||||
# define RADEON_TXFORMAT_AI88 (1 << 0)
|
||||
# define RADEON_TXFORMAT_RGB332 (2 << 0)
|
||||
# define RADEON_TXFORMAT_ARGB1555 (3 << 0)
|
||||
# define RADEON_TXFORMAT_RGB565 (4 << 0)
|
||||
# define RADEON_TXFORMAT_ARGB4444 (5 << 0)
|
||||
# define RADEON_TXFORMAT_ARGB8888 (6 << 0)
|
||||
# define RADEON_TXFORMAT_RGBA8888 (7 << 0)
|
||||
# define RADEON_TXFORMAT_Y8 (8 << 0)
|
||||
# define RADEON_TXFORMAT_VYUY422 (10 << 0)
|
||||
# define RADEON_TXFORMAT_YVYU422 (11 << 0)
|
||||
# define RADEON_TXFORMAT_DXT1 (12 << 0)
|
||||
# define RADEON_TXFORMAT_DXT23 (14 << 0)
|
||||
# define RADEON_TXFORMAT_DXT45 (15 << 0)
|
||||
# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0)
|
||||
# define RADEON_TXFORMAT_FORMAT_SHIFT 0
|
||||
# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5)
|
||||
# define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6)
|
||||
# define RADEON_TXFORMAT_NON_POWER2 (1 << 7)
|
||||
# define RADEON_TXFORMAT_WIDTH_MASK (15 << 8)
|
||||
# define RADEON_TXFORMAT_WIDTH_SHIFT 8
|
||||
# define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12)
|
||||
# define RADEON_TXFORMAT_HEIGHT_SHIFT 12
|
||||
# define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16)
|
||||
# define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16
|
||||
# define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20)
|
||||
# define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20
|
||||
# define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)
|
||||
# define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24)
|
||||
# define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)
|
||||
# define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)
|
||||
# define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26)
|
||||
# define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26)
|
||||
# define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26)
|
||||
# define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26)
|
||||
# define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)
|
||||
# define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)
|
||||
# define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)
|
||||
# define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31)
|
||||
|
||||
#define RADEON_REG_PP_TXOFFSET_0 0x1c5c
|
||||
#define RADEON_REG_PP_TXOFFSET_1 0x1c74
|
||||
#define RADEON_REG_PP_TXOFFSET_2 0x1c8c
|
||||
# define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0)
|
||||
# define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0)
|
||||
# define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0)
|
||||
# define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
|
||||
# define RADEON_TXO_MACRO_LINEAR (0 << 2)
|
||||
# define RADEON_TXO_MACRO_TILE (1 << 2)
|
||||
# define RADEON_TXO_MICRO_LINEAR (0 << 3)
|
||||
# define RADEON_TXO_MICRO_TILE_X2 (1 << 3)
|
||||
# define RADEON_TXO_MICRO_TILE_OPT (2 << 3)
|
||||
# define RADEON_TXO_OFFSET_MASK 0xffffffe0
|
||||
# define RADEON_TXO_OFFSET_SHIFT 5
|
||||
|
||||
#define RADEON_REG_PP_TXCBLEND_0 0x1c60
|
||||
#define RADEON_REG_PP_TXCBLEND_1 0x1c78
|
||||
#define RADEON_REG_PP_TXCBLEND_2 0x1c90
|
||||
# define RADEON_COLOR_ARG_A_SHIFT 0
|
||||
# define RADEON_COLOR_ARG_A_MASK (0x1f << 0)
|
||||
# define RADEON_COLOR_ARG_A_ZERO (0 << 0)
|
||||
# define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0)
|
||||
# define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0)
|
||||
# define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0)
|
||||
# define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0)
|
||||
# define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0)
|
||||
# define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0)
|
||||
# define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0)
|
||||
# define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0)
|
||||
# define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0)
|
||||
# define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0)
|
||||
# define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0)
|
||||
# define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0)
|
||||
# define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0)
|
||||
# define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0)
|
||||
# define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0)
|
||||
# define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0)
|
||||
# define RADEON_COLOR_ARG_B_SHIFT 5
|
||||
# define RADEON_COLOR_ARG_B_MASK (0x1f << 5)
|
||||
# define RADEON_COLOR_ARG_B_ZERO (0 << 5)
|
||||
# define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5)
|
||||
# define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5)
|
||||
# define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5)
|
||||
# define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5)
|
||||
# define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5)
|
||||
# define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5)
|
||||
# define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5)
|
||||
# define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5)
|
||||
# define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5)
|
||||
# define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5)
|
||||
# define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5)
|
||||
# define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5)
|
||||
# define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5)
|
||||
# define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5)
|
||||
# define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5)
|
||||
# define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5)
|
||||
# define RADEON_COLOR_ARG_C_SHIFT 10
|
||||
# define RADEON_COLOR_ARG_C_MASK (0x1f << 10)
|
||||
# define RADEON_COLOR_ARG_C_ZERO (0 << 10)
|
||||
# define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10)
|
||||
# define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10)
|
||||
# define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10)
|
||||
# define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10)
|
||||
# define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10)
|
||||
# define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10)
|
||||
# define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10)
|
||||
# define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10)
|
||||
# define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10)
|
||||
# define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10)
|
||||
# define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10)
|
||||
# define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10)
|
||||
# define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10)
|
||||
# define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10)
|
||||
# define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10)
|
||||
# define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10)
|
||||
# define RADEON_COMP_ARG_A (1 << 15)
|
||||
# define RADEON_COMP_ARG_A_SHIFT 15
|
||||
# define RADEON_COMP_ARG_B (1 << 16)
|
||||
# define RADEON_COMP_ARG_B_SHIFT 16
|
||||
# define RADEON_COMP_ARG_C (1 << 17)
|
||||
# define RADEON_COMP_ARG_C_SHIFT 17
|
||||
# define RADEON_BLEND_CTL_MASK (7 << 18)
|
||||
# define RADEON_BLEND_CTL_ADD (0 << 18)
|
||||
# define RADEON_BLEND_CTL_SUBTRACT (1 << 18)
|
||||
# define RADEON_BLEND_CTL_ADDSIGNED (2 << 18)
|
||||
# define RADEON_BLEND_CTL_BLEND (3 << 18)
|
||||
# define RADEON_BLEND_CTL_DOT3 (4 << 18)
|
||||
# define RADEON_SCALE_SHIFT 21
|
||||
# define RADEON_SCALE_MASK (3 << 21)
|
||||
# define RADEON_SCALE_1X (0 << 21)
|
||||
# define RADEON_SCALE_2X (1 << 21)
|
||||
# define RADEON_SCALE_4X (2 << 21)
|
||||
# define RADEON_CLAMP_TX (1 << 23)
|
||||
# define RADEON_T0_EQ_TCUR (1 << 24)
|
||||
# define RADEON_T1_EQ_TCUR (1 << 25)
|
||||
# define RADEON_T2_EQ_TCUR (1 << 26)
|
||||
# define RADEON_T3_EQ_TCUR (1 << 27)
|
||||
# define RADEON_COLOR_ARG_MASK 0x1f
|
||||
# define RADEON_COMP_ARG_SHIFT 15
|
||||
|
||||
#define RADEON_REG_PP_TXABLEND_0 0x1c64
|
||||
#define RADEON_REG_PP_TXABLEND_1 0x1c7c
|
||||
#define RADEON_REG_PP_TXABLEND_2 0x1c94
|
||||
# define RADEON_ALPHA_ARG_A_SHIFT 0
|
||||
# define RADEON_ALPHA_ARG_A_MASK (0xf << 0)
|
||||
# define RADEON_ALPHA_ARG_A_ZERO (0 << 0)
|
||||
# define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0)
|
||||
# define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0)
|
||||
# define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0)
|
||||
# define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0)
|
||||
# define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0)
|
||||
# define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0)
|
||||
# define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0)
|
||||
# define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0)
|
||||
# define RADEON_ALPHA_ARG_B_SHIFT 4
|
||||
# define RADEON_ALPHA_ARG_B_MASK (0xf << 4)
|
||||
# define RADEON_ALPHA_ARG_B_ZERO (0 << 4)
|
||||
# define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4)
|
||||
# define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4)
|
||||
# define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4)
|
||||
# define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4)
|
||||
# define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4)
|
||||
# define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4)
|
||||
# define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4)
|
||||
# define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4)
|
||||
# define RADEON_ALPHA_ARG_C_SHIFT 8
|
||||
# define RADEON_ALPHA_ARG_C_MASK (0xf << 8)
|
||||
# define RADEON_ALPHA_ARG_C_ZERO (0 << 8)
|
||||
# define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8)
|
||||
# define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8)
|
||||
# define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8)
|
||||
# define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8)
|
||||
# define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8)
|
||||
# define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8)
|
||||
# define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8)
|
||||
# define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8)
|
||||
# define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9)
|
||||
# define RADEON_ALPHA_ARG_MASK 0xf
|
||||
|
||||
#define RADEON_REG_PP_TFACTOR_0 0x1c68
|
||||
#define RADEON_REG_PP_TFACTOR_1 0x1c80
|
||||
#define RADEON_REG_PP_TFACTOR_2 0x1c98
|
||||
|
||||
#define RADEON_REG_PP_TEX_SIZE_0 0x1d04 /* NPOT */
|
||||
#define RADEON_REG_PP_TEX_SIZE_1 0x1d0c
|
||||
#define RADEON_REG_PP_TEX_SIZE_2 0x1d14
|
||||
# define RADEON_TEX_USIZE_MASK (0x7ff << 0)
|
||||
# define RADEON_TEX_USIZE_SHIFT 0
|
||||
# define RADEON_TEX_VSIZE_MASK (0x7ff << 16)
|
||||
# define RADEON_TEX_VSIZE_SHIFT 16
|
||||
# define RADEON_SIGNED_RGB_MASK (1 << 30)
|
||||
# define RADEON_SIGNED_RGB_SHIFT 30
|
||||
# define RADEON_SIGNED_ALPHA_MASK (1 << 31)
|
||||
# define RADEON_SIGNED_ALPHA_SHIFT 31
|
||||
|
||||
#define RADEON_REG_PP_TEX_PITCH_0 0x1d08 /* NPOT */
|
||||
#define RADEON_REG_PP_TEX_PITCH_1 0x1d10 /* NPOT */
|
||||
#define RADEON_REG_PP_TEX_PITCH_2 0x1d18 /* NPOT */
|
||||
/* note: bits 13-5: 32 byte aligned stride of texture map */
|
||||
|
||||
#define RADEON_REG_RB3D_PLANEMASK 0x1d84
|
||||
|
||||
#define RADEON_REG_SE_CNTL_STATUS 0x2140
|
||||
# define RADEON_VC_NO_SWAP (0 << 0)
|
||||
# define RADEON_VC_16BIT_SWAP (1 << 0)
|
||||
# define RADEON_VC_32BIT_SWAP (2 << 0)
|
||||
# define RADEON_VC_HALF_DWORD_SWAP (3 << 0)
|
||||
# define RADEON_TCL_BYPASS (1 << 8)
|
||||
|
||||
#define RADEON_REG_RE_TOP_LEFT 0x26c0
|
||||
|
||||
#define RADEON_REG_RB2D_DSTCACHE_CTLSTAT 0x342c
|
||||
# define RADEON_RB2D_DC_FLUSH (3 << 0)
|
||||
# define RADEON_RB2D_DC_FREE (3 << 2)
|
||||
|
|
@ -82,6 +529,74 @@
|
|||
#define RADEON_CP_PACKET0 0x00000000
|
||||
#define RADEON_CP_PACKET1 0x40000000
|
||||
#define RADEON_CP_PACKET2 0x80000000
|
||||
#define RADEON_CP_PACKET3_NOP 0xC0001000
|
||||
#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900
|
||||
#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00
|
||||
#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00
|
||||
#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300
|
||||
#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400
|
||||
#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600
|
||||
#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800
|
||||
#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900
|
||||
#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00
|
||||
#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00
|
||||
#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00
|
||||
#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100
|
||||
#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200
|
||||
#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300
|
||||
#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400
|
||||
#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500
|
||||
#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800
|
||||
#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00
|
||||
#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00
|
||||
#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00
|
||||
|
||||
#define RADEON_CP_VC_FRMT_XY 0x00000000
|
||||
#define RADEON_CP_VC_FRMT_W0 0x00000001
|
||||
#define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002
|
||||
#define RADEON_CP_VC_FRMT_FPALPHA 0x00000004
|
||||
#define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008
|
||||
#define RADEON_CP_VC_FRMT_FPSPEC 0x00000010
|
||||
#define RADEON_CP_VC_FRMT_FPFOG 0x00000020
|
||||
#define RADEON_CP_VC_FRMT_PKSPEC 0x00000040
|
||||
#define RADEON_CP_VC_FRMT_ST0 0x00000080
|
||||
#define RADEON_CP_VC_FRMT_ST1 0x00000100
|
||||
#define RADEON_CP_VC_FRMT_Q1 0x00000200
|
||||
#define RADEON_CP_VC_FRMT_ST2 0x00000400
|
||||
#define RADEON_CP_VC_FRMT_Q2 0x00000800
|
||||
#define RADEON_CP_VC_FRMT_ST3 0x00001000
|
||||
#define RADEON_CP_VC_FRMT_Q3 0x00002000
|
||||
#define RADEON_CP_VC_FRMT_Q0 0x00004000
|
||||
#define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000
|
||||
#define RADEON_CP_VC_FRMT_N0 0x00040000
|
||||
#define RADEON_CP_VC_FRMT_XY1 0x08000000
|
||||
#define RADEON_CP_VC_FRMT_Z1 0x10000000
|
||||
#define RADEON_CP_VC_FRMT_W1 0x20000000
|
||||
#define RADEON_CP_VC_FRMT_N1 0x40000000
|
||||
#define RADEON_CP_VC_FRMT_Z 0x80000000
|
||||
|
||||
#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000
|
||||
#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001
|
||||
#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002
|
||||
#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003
|
||||
#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
|
||||
#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
|
||||
#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
|
||||
#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007
|
||||
#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008
|
||||
#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009
|
||||
#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a
|
||||
#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010
|
||||
#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020
|
||||
#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030
|
||||
#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000
|
||||
#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040
|
||||
#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080
|
||||
#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000
|
||||
#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100
|
||||
#define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000
|
||||
#define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200
|
||||
#define RADEON_CP_VC_CNTL_NUM_SHIFT 16
|
||||
|
||||
#define R128_REG_PC_NGUI_CTLSTAT 0x0184
|
||||
# define R128_PC_BUSY (1 << 31)
|
||||
|
|
|
|||
398
hw/kdrive/ati/radeon_composite.c
Normal file
398
hw/kdrive/ati/radeon_composite.c
Normal file
|
|
@ -0,0 +1,398 @@
|
|||
/*
|
||||
* $Id$
|
||||
*
|
||||
* Copyright © 2003 Eric Anholt
|
||||
*
|
||||
* Permission to use, copy, modify, distribute, and sell this software and its
|
||||
* documentation for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice appear in all copies and that both that
|
||||
* copyright notice and this permission notice appear in supporting
|
||||
* documentation, and that the name of Eric Anholt not be used in
|
||||
* advertising or publicity pertaining to distribution of the software without
|
||||
* specific, written prior permission. Eric Anholt makes no
|
||||
* representations about the suitability of this software for any purpose. It
|
||||
* is provided "as is" without express or implied warranty.
|
||||
*
|
||||
* ERIC ANHOLT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
|
||||
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
|
||||
* EVENT SHALL ERIC ANHOLT BE LIABLE FOR ANY SPECIAL, INDIRECT OR
|
||||
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
|
||||
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
/* $Header$ */
|
||||
|
||||
#ifdef HAVE_CONFIG_H
|
||||
#include <config.h>
|
||||
#endif
|
||||
#include "ati.h"
|
||||
#include "ati_reg.h"
|
||||
#include "ati_draw.h"
|
||||
#include "radeon_common.h"
|
||||
#include "r128_common.h"
|
||||
#include "ati_sarea.h"
|
||||
|
||||
#define TAG(x) x##DMA
|
||||
#define LOCALS (void)atic; \
|
||||
RING_LOCALS
|
||||
#define BEGIN(x) BEGIN_RING(x * 2)
|
||||
#define OUT_REG(reg, val) OUT_RING_REG(reg, val)
|
||||
#define END() ADVANCE_RING()
|
||||
|
||||
extern ATIScreenInfo *accel_atis;
|
||||
|
||||
static CARD32 RadeonBlendOp[] = {
|
||||
/* Clear */
|
||||
RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ZERO,
|
||||
/* Src */
|
||||
RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO,
|
||||
/* Dst */
|
||||
RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE,
|
||||
/* Over */
|
||||
RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA,
|
||||
/* OverReverse */
|
||||
RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE,
|
||||
/* In */
|
||||
RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO,
|
||||
/* InReverse */
|
||||
RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_SRC_ALPHA,
|
||||
/* Out */
|
||||
RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO,
|
||||
/* OutReverse */
|
||||
RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA,
|
||||
/* Atop */
|
||||
RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA,
|
||||
/* AtopReverse */
|
||||
RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_SRC_ALPHA,
|
||||
/* Xor */
|
||||
RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA,
|
||||
/* Add */
|
||||
RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE,
|
||||
};
|
||||
|
||||
/* Compute log base 2 of val. */
|
||||
static int
|
||||
ATILog2(int val)
|
||||
{
|
||||
int bits;
|
||||
|
||||
if (!val)
|
||||
return 1;
|
||||
for (bits = 0; val != 0; val >>= 1, ++bits)
|
||||
;
|
||||
return bits;
|
||||
}
|
||||
|
||||
static Bool
|
||||
RadeonTextureSetup(PicturePtr pPict, PixmapPtr pPix, int unit)
|
||||
{
|
||||
ATIScreenInfo *atis = accel_atis;
|
||||
ATICardInfo *atic = atis->atic;
|
||||
KdScreenPriv(pPix->drawable.pScreen);
|
||||
CARD32 txformat, txoffset, txpitch;
|
||||
int w = pPict->pDrawable->width;
|
||||
int h = pPict->pDrawable->height;
|
||||
LOCALS;
|
||||
|
||||
if ((w > 0x7ff) || (h > 0x7ff))
|
||||
ATI_FALLBACK(("Picture w/h too large (%dx%d)\n", w, h));
|
||||
|
||||
switch (pPict->format) {
|
||||
case PICT_a8r8g8b8:
|
||||
txformat = RADEON_TXFORMAT_ARGB8888 |
|
||||
RADEON_TXFORMAT_ALPHA_IN_MAP;
|
||||
break;
|
||||
case PICT_x8r8g8b8:
|
||||
txformat = RADEON_TXFORMAT_ARGB8888;
|
||||
break;
|
||||
case PICT_r5g6b5:
|
||||
txformat = RADEON_TXFORMAT_RGB565;
|
||||
break;
|
||||
case PICT_a8:
|
||||
txformat = RADEON_TXFORMAT_I8 | RADEON_TXFORMAT_ALPHA_IN_MAP;
|
||||
break;
|
||||
default:
|
||||
ATI_FALLBACK(("Unsupported picture format 0x%x\n",
|
||||
pPict->format));
|
||||
}
|
||||
if (pPict->repeat) {
|
||||
if ((w & (w - 1)) != 0 || (h & (h - 1)) != 0)
|
||||
ATI_FALLBACK(("NPOT repeat unsupported (%dx%d)\n", w,
|
||||
h));
|
||||
|
||||
txformat |= (ATILog2(w) - 1) << RADEON_TXFORMAT_WIDTH_SHIFT;
|
||||
txformat |= (ATILog2(h) - 1) << RADEON_TXFORMAT_HEIGHT_SHIFT;
|
||||
} else
|
||||
txformat |= RADEON_TXFORMAT_NON_POWER2;
|
||||
|
||||
txpitch = pPix->devKind;
|
||||
txoffset = ((CARD8 *)pPix->devPrivate.ptr -
|
||||
pScreenPriv->screen->memory_base);
|
||||
|
||||
if ((txoffset & 0x3f) != 0)
|
||||
ATI_FALLBACK(("Bad texture offset 0x%x\n", txoffset));
|
||||
if ((txpitch & 0x3f) != 0)
|
||||
ATI_FALLBACK(("Bad texture pitch 0x%x\n", txpitch));
|
||||
|
||||
/* RADEON_REG_PP_TXFILTER_0, RADEON_REG_PP_TXFORMAT_0,
|
||||
* RADEON_REG_PP_TXOFFSET_0
|
||||
*/
|
||||
BEGIN_RING(4);
|
||||
OUT_RING(DMA_PACKET0(RADEON_REG_PP_TXFILTER_0 + 0x18 * unit, 2));
|
||||
OUT_RING(0);
|
||||
OUT_RING(txformat);
|
||||
OUT_RING(txoffset);
|
||||
ADVANCE_RING();
|
||||
|
||||
/* RADEON_REG_PP_TEX_SIZE_0, RADEON_REG_PP_TEX_PITCH_0 */
|
||||
BEGIN_RING(3);
|
||||
OUT_RING(DMA_PACKET0(RADEON_REG_PP_TEX_SIZE_0 + 0x8 * unit, 1));
|
||||
OUT_RING((pPix->drawable.width - 1) |
|
||||
((pPix->drawable.height - 1) << RADEON_TEX_VSIZE_SHIFT));
|
||||
OUT_RING(txpitch - 32);
|
||||
ADVANCE_RING();
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
Bool
|
||||
RadeonPrepareComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
|
||||
PicturePtr pDstPicture, PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst)
|
||||
{
|
||||
KdScreenPriv(pDst->drawable.pScreen);
|
||||
ATIScreenInfo(pScreenPriv);
|
||||
ATICardInfo(pScreenPriv);
|
||||
CARD32 dst_format, dst_offset, dst_pitch;
|
||||
CARD32 pp_cntl;
|
||||
int pixel_shift;
|
||||
LOCALS;
|
||||
|
||||
/*ErrorF("RadeonPrepareComposite\n");*/
|
||||
|
||||
/* Check for unsupported compositing operations. */
|
||||
if (op >= sizeof(RadeonBlendOp) / sizeof(RadeonBlendOp[0]))
|
||||
ATI_FALLBACK(("Unsupported Composite op 0x%x\n", op));
|
||||
|
||||
accel_atis = atis;
|
||||
|
||||
switch (pDstPicture->format) {
|
||||
case PICT_r5g6b5:
|
||||
dst_format = RADEON_COLOR_FORMAT_RGB565;
|
||||
pixel_shift = 1;
|
||||
break;
|
||||
case PICT_a1r5g5b5:
|
||||
dst_format = RADEON_COLOR_FORMAT_ARGB1555;
|
||||
pixel_shift = 1;
|
||||
break;
|
||||
case PICT_a8r8g8b8:
|
||||
case PICT_x8r8g8b8:
|
||||
dst_format = RADEON_COLOR_FORMAT_ARGB8888;
|
||||
pixel_shift = 2;
|
||||
break;
|
||||
default:
|
||||
ATI_FALLBACK(("Unsupported dest format 0x%x\n",
|
||||
pDstPicture->format));
|
||||
}
|
||||
|
||||
dst_offset = ((CARD8 *)pDst->devPrivate.ptr -
|
||||
pScreenPriv->screen->memory_base);
|
||||
dst_pitch = pDst->devKind;
|
||||
if ((dst_offset & 0xff) != 0)
|
||||
ATI_FALLBACK(("Bad destination offset 0x%x\n", dst_offset));
|
||||
if (((dst_pitch >> pixel_shift) & 0x7) != 0)
|
||||
ATI_FALLBACK(("Bad destination pitch 0x%x\n", dst_pitch));
|
||||
|
||||
if (!RadeonTextureSetup(pSrcPicture, pSrc, 0))
|
||||
return FALSE;
|
||||
pp_cntl = RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE;
|
||||
|
||||
if (pMask != NULL) {
|
||||
if (!RadeonTextureSetup(pMaskPicture, pMask, 1))
|
||||
return FALSE;
|
||||
pp_cntl |= RADEON_TEX_1_ENABLE;
|
||||
}
|
||||
|
||||
BEGIN(2);
|
||||
OUT_REG(RADEON_REG_RE_TOP_LEFT, 0);
|
||||
OUT_REG(RADEON_REG_RE_WIDTH_HEIGHT, 0xffffffff);
|
||||
END();
|
||||
|
||||
BEGIN(11);
|
||||
OUT_REG(RADEON_REG_PP_CNTL, pp_cntl);
|
||||
OUT_REG(RADEON_REG_RB3D_CNTL, dst_format | RADEON_ALPHA_BLEND_ENABLE);
|
||||
/* COLORPITCH is multiples of 8 pixels, but located at the 3rd bit */
|
||||
OUT_REG(RADEON_REG_RB3D_COLORPITCH, (dst_pitch >> pixel_shift));
|
||||
OUT_REG(RADEON_REG_RB3D_COLOROFFSET, dst_offset);
|
||||
OUT_REG(RADEON_REG_RB3D_PLANEMASK, 0xffffffff);
|
||||
OUT_REG(RADEON_REG_SE_CNTL, RADEON_FFACE_CULL_CCW | RADEON_FFACE_SOLID |
|
||||
RADEON_VTX_PIX_CENTER_OGL);
|
||||
OUT_REG(RADEON_REG_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
|
||||
OUT_REG(RADEON_REG_SE_COORD_FMT,
|
||||
RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
|
||||
RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
|
||||
RADEON_VTX_ST0_NONPARAMETRIC |
|
||||
RADEON_VTX_ST1_NONPARAMETRIC |
|
||||
RADEON_TEX1_W_ROUTING_USE_W0);
|
||||
if (pMask != NULL) {
|
||||
/* IN operator: Multiply src by mask components or mask alpha.
|
||||
* BLEND_CTL_ADD is A * B + C
|
||||
*/
|
||||
if (pMaskPicture->componentAlpha)
|
||||
OUT_REG(RADEON_REG_PP_TXCBLEND_0,
|
||||
RADEON_COLOR_ARG_A_T0_COLOR |
|
||||
RADEON_COLOR_ARG_B_T1_COLOR |
|
||||
RADEON_COLOR_ARG_C_ZERO |
|
||||
RADEON_BLEND_CTL_ADD |
|
||||
RADEON_CLAMP_TX);
|
||||
else
|
||||
OUT_REG(RADEON_REG_PP_TXCBLEND_0,
|
||||
RADEON_COLOR_ARG_A_T0_COLOR |
|
||||
RADEON_COLOR_ARG_B_T1_ALPHA |
|
||||
RADEON_COLOR_ARG_C_ZERO |
|
||||
RADEON_BLEND_CTL_ADD |
|
||||
RADEON_CLAMP_TX);
|
||||
OUT_REG(RADEON_REG_PP_TXABLEND_0,
|
||||
RADEON_ALPHA_ARG_A_T0_ALPHA |
|
||||
RADEON_ALPHA_ARG_B_T1_ALPHA |
|
||||
RADEON_ALPHA_ARG_C_ZERO |
|
||||
RADEON_BLEND_CTL_ADD);
|
||||
} else {
|
||||
OUT_REG(RADEON_REG_PP_TXCBLEND_0,
|
||||
RADEON_COLOR_ARG_A_ZERO |
|
||||
RADEON_COLOR_ARG_B_ZERO |
|
||||
RADEON_COLOR_ARG_C_T0_COLOR |
|
||||
RADEON_BLEND_CTL_ADD |
|
||||
RADEON_CLAMP_TX);
|
||||
OUT_REG(RADEON_REG_PP_TXABLEND_0,
|
||||
RADEON_ALPHA_ARG_A_ZERO |
|
||||
RADEON_ALPHA_ARG_B_ZERO |
|
||||
RADEON_ALPHA_ARG_C_T0_ALPHA |
|
||||
RADEON_BLEND_CTL_ADD);
|
||||
}
|
||||
/* Op operator. */
|
||||
OUT_REG(RADEON_RB3D_BLENDCNTL, RadeonBlendOp[op]);
|
||||
END();
|
||||
|
||||
RadeonSwitchTo3D();
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
union intfloat {
|
||||
float f;
|
||||
CARD32 i;
|
||||
};
|
||||
|
||||
struct blend_vertex {
|
||||
union intfloat x, y, z;
|
||||
union intfloat s0, t0;
|
||||
union intfloat s1, t1;
|
||||
};
|
||||
|
||||
#define VTX_REG_COUNT 7
|
||||
|
||||
#define VTX_OUT(vtx) \
|
||||
do { \
|
||||
OUT_RING(vtx.x.i); \
|
||||
OUT_RING(vtx.y.i); \
|
||||
OUT_RING(vtx.z.i); \
|
||||
OUT_RING(vtx.s0.i); \
|
||||
OUT_RING(vtx.t0.i); \
|
||||
OUT_RING(vtx.s1.i); \
|
||||
OUT_RING(vtx.t1.i); \
|
||||
/*ErrorF("%f,%f,%f %f,%f %f,%f\n", vtx.x.f, vtx.y.f, vtx.z.f, vtx.s0.f, \
|
||||
vtx.t0.f, vtx.s1.f, vtx.t1.f);*/ \
|
||||
} while (0)
|
||||
|
||||
void
|
||||
RadeonComposite(int srcX, int srcY, int maskX, int maskY, int dstX, int dstY,
|
||||
int w, int h)
|
||||
{
|
||||
ATIScreenInfo *atis = accel_atis;
|
||||
ATICardInfo *atic = atis->atic;
|
||||
LOCALS;
|
||||
struct blend_vertex vtx[4];
|
||||
|
||||
/*ErrorF("RadeonComposite %d %d %d %d %d %d\n", srcX, srcY, maskX, maskY,
|
||||
dstX, dstY, w, h);*/
|
||||
BEGIN_RING(3 + 6 * VTX_REG_COUNT);
|
||||
OUT_RING(RADEON_CP_PACKET3_3D_DRAW_IMMD |
|
||||
((6 * VTX_REG_COUNT + 1) << 16));
|
||||
OUT_RING(RADEON_CP_VC_FRMT_XY |
|
||||
RADEON_CP_VC_FRMT_Z |
|
||||
RADEON_CP_VC_FRMT_ST0 |
|
||||
RADEON_CP_VC_FRMT_ST1);
|
||||
OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST |
|
||||
RADEON_CP_VC_CNTL_PRIM_WALK_RING |
|
||||
RADEON_CP_VC_CNTL_MAOS_ENABLE |
|
||||
RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
|
||||
(6 << RADEON_CP_VC_CNTL_NUM_SHIFT));
|
||||
|
||||
vtx[0].x.f = dstX;
|
||||
vtx[0].y.f = dstY;
|
||||
vtx[0].z.f = 0.5;
|
||||
vtx[0].s0.f = srcX;
|
||||
vtx[0].t0.f = srcY;
|
||||
vtx[0].s1.f = maskX;
|
||||
vtx[0].t1.f = maskY;
|
||||
|
||||
vtx[1].x.f = dstX;
|
||||
vtx[1].y.f = dstY + h;
|
||||
vtx[1].z.f = 0.5;
|
||||
vtx[1].s0.f = srcX;
|
||||
vtx[1].t0.f = srcY + h;
|
||||
vtx[1].s1.f = maskX;
|
||||
vtx[1].t1.f = maskY + h;
|
||||
|
||||
vtx[2].x.f = dstX + w;
|
||||
vtx[2].y.f = dstY + h;
|
||||
vtx[2].z.f = 0.5;
|
||||
vtx[2].s0.f = srcX + w;
|
||||
vtx[2].t0.f = srcY + h;
|
||||
vtx[2].s1.f = maskX + w;
|
||||
vtx[2].t1.f = maskY + h;
|
||||
|
||||
vtx[3].x.f = dstX + w;
|
||||
vtx[3].y.f = dstY;
|
||||
vtx[3].z.f = 0.5;
|
||||
vtx[3].s0.f = srcX + w;
|
||||
vtx[3].t0.f = srcY;
|
||||
vtx[3].s1.f = maskX + w;
|
||||
vtx[3].t1.f = maskY;
|
||||
|
||||
VTX_OUT(vtx[0]);
|
||||
VTX_OUT(vtx[1]);
|
||||
VTX_OUT(vtx[2]);
|
||||
VTX_OUT(vtx[0]);
|
||||
VTX_OUT(vtx[2]);
|
||||
VTX_OUT(vtx[3]);
|
||||
|
||||
ADVANCE_RING();
|
||||
}
|
||||
|
||||
void
|
||||
RadeonDoneComposite(void)
|
||||
{
|
||||
/*ErrorF("RadeonDoneComposite\n");*/
|
||||
}
|
||||
|
||||
Bool
|
||||
RadeonPrepareBlend(int op, PicturePtr pSrcPicture, PicturePtr pDstPicture,
|
||||
PixmapPtr pSrc, PixmapPtr pDst)
|
||||
{
|
||||
return RadeonPrepareComposite(op, pSrcPicture, NULL, pDstPicture, pSrc,
|
||||
NULL, pDst);
|
||||
}
|
||||
|
||||
void
|
||||
RadeonBlend(int srcX, int srcY, int dstX, int dstY, int width, int height)
|
||||
{
|
||||
RadeonComposite(srcX, srcY, 0, 0, dstX, dstY, width, height);
|
||||
}
|
||||
|
||||
void
|
||||
RadeonDoneBlend(void)
|
||||
{
|
||||
RadeonDoneComposite();
|
||||
}
|
||||
|
|
@ -320,8 +320,8 @@ kaaComposite(CARD8 op,
|
|||
ySrc += pSrc->pDrawable->y;
|
||||
|
||||
if (!miComputeCompositeRegion (®ion, pSrc, pMask, pDst,
|
||||
xSrc, ySrc, xMask, yMask, xDst, yDst,
|
||||
width, height))
|
||||
xSrc, ySrc, xMask, yMask, xDst,
|
||||
yDst, width, height))
|
||||
return;
|
||||
|
||||
|
||||
|
|
@ -396,6 +396,87 @@ kaaComposite(CARD8 op,
|
|||
return;
|
||||
}
|
||||
}
|
||||
if (pScreenPriv->enabled && pKaaScr->info->PrepareComposite &&
|
||||
!pSrc->alphaMap && (!pMask || !pMask->alphaMap) && !pDst->alphaMap)
|
||||
{
|
||||
/* Catch-all Composite case */
|
||||
RegionRec region;
|
||||
BoxPtr pbox;
|
||||
int nbox;
|
||||
int src_off_x, src_off_y, mask_off_x, mask_off_y, dst_off_x, dst_off_y;
|
||||
PixmapPtr pSrcPix, pMaskPix = NULL, pDstPix;
|
||||
|
||||
xDst += pDst->pDrawable->x;
|
||||
yDst += pDst->pDrawable->y;
|
||||
|
||||
if (pMask) {
|
||||
xMask += pMask->pDrawable->x;
|
||||
yMask += pMask->pDrawable->y;
|
||||
}
|
||||
|
||||
xSrc += pSrc->pDrawable->x;
|
||||
ySrc += pSrc->pDrawable->y;
|
||||
|
||||
if (!miComputeCompositeRegion (®ion, pSrc, pMask, pDst,
|
||||
xSrc, ySrc, xMask, yMask, xDst, yDst,
|
||||
width, height))
|
||||
return;
|
||||
|
||||
|
||||
/* Migrate pixmaps to same place as destination */
|
||||
if (pSrc->pDrawable->type == DRAWABLE_PIXMAP)
|
||||
kaaPixmapUseScreen ((PixmapPtr) pSrc->pDrawable);
|
||||
if (pMask && pMask->pDrawable->type == DRAWABLE_PIXMAP)
|
||||
kaaPixmapUseScreen ((PixmapPtr) pMask->pDrawable);
|
||||
if (pDst->pDrawable->type == DRAWABLE_PIXMAP)
|
||||
kaaPixmapUseScreen ((PixmapPtr) pDst->pDrawable);
|
||||
|
||||
pSrcPix = kaaGetOffscreenPixmap (pSrc->pDrawable, &src_off_x,
|
||||
&src_off_y);
|
||||
pDstPix = kaaGetOffscreenPixmap (pDst->pDrawable, &dst_off_x,
|
||||
&dst_off_y);
|
||||
if (!pSrcPix || !pDstPix)
|
||||
goto software2;
|
||||
if (pMask) {
|
||||
pMaskPix = kaaGetOffscreenPixmap (pMask->pDrawable, &mask_off_x,
|
||||
&mask_off_y);
|
||||
if (!pMaskPix)
|
||||
goto software2;
|
||||
}
|
||||
|
||||
if (!(*pKaaScr->info->PrepareComposite) (op, pSrc, pMask, pDst, pSrcPix,
|
||||
pMaskPix, pDstPix))
|
||||
{
|
||||
goto software;
|
||||
}
|
||||
|
||||
nbox = REGION_NUM_RECTS(®ion);
|
||||
pbox = REGION_RECTS(®ion);
|
||||
|
||||
xMask -= xDst;
|
||||
yMask -= yDst;
|
||||
|
||||
xSrc -= xDst;
|
||||
ySrc -= yDst;
|
||||
|
||||
while (nbox--)
|
||||
{
|
||||
(*pKaaScr->info->Composite) (pbox->x1 + xSrc + src_off_x,
|
||||
pbox->y1 + ySrc + src_off_y,
|
||||
pbox->x1 + mask_off_x,
|
||||
pbox->y1 + mask_off_y,
|
||||
pbox->x1 + dst_off_x,
|
||||
pbox->y1 + dst_off_y,
|
||||
pbox->x2 - pbox->x1,
|
||||
pbox->y2 - pbox->y1);
|
||||
pbox++;
|
||||
}
|
||||
|
||||
(*pKaaScr->info->DoneBlend) ();
|
||||
KdMarkSync(pDst->pDrawable->pScreen);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
software:
|
||||
if (pSrc->pDrawable->type == DRAWABLE_PIXMAP)
|
||||
|
|
|
|||
|
|
@ -345,6 +345,23 @@ typedef struct _KaaScreenInfo {
|
|||
int width,
|
||||
int height);
|
||||
void (*DoneBlend) (void);
|
||||
|
||||
Bool (*PrepareComposite) (int op,
|
||||
PicturePtr pSrcPicture,
|
||||
PicturePtr pMaskPicture,
|
||||
PicturePtr pDstPicture,
|
||||
PixmapPtr pSrc,
|
||||
PixmapPtr pMask,
|
||||
PixmapPtr pDst);
|
||||
void (*Composite) (int srcX,
|
||||
int srcY,
|
||||
int maskX,
|
||||
int maskY,
|
||||
int dstX,
|
||||
int dstY,
|
||||
int width,
|
||||
int height);
|
||||
void (*DoneComposite) (void);
|
||||
} KaaScreenInfoRec, *KaaScreenInfoPtr;
|
||||
|
||||
#define KAA_OFFSCREEN_PIXMAPS (1 << 0)
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user