1139 lines
33 KiB
C
1139 lines
33 KiB
C
/*
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* $Id$
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*
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* Copyright © 2003 Eric Anholt
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that
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* copyright notice and this permission notice appear in supporting
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* documentation, and that the name of Eric Anholt not be used in
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* advertising or publicity pertaining to distribution of the software without
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* specific, written prior permission. Eric Anholt makes no
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* representations about the suitability of this software for any purpose. It
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* is provided "as is" without express or implied warranty.
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*
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* ERIC ANHOLT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL ERIC ANHOLT BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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/* $Header$ */
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#ifdef HAVE_CONFIG_H
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#include <config.h>
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#endif
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#include "ati.h"
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#include "ati_reg.h"
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#include "ati_dma.h"
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#include "ati_dri.h"
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#include "ati_dripriv.h"
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#include "sarea.h"
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#include "ati_sarea.h"
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#include "ati_draw.h"
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#include "r128_common.h"
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#include "radeon_common.h"
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/* ?? HACK - for now, put this here... */
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/* ?? Alpha - this may need to be a variable to handle UP1x00 vs TITAN */
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#if defined(__alpha__)
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# define DRM_PAGE_SIZE 8192
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#elif defined(__ia64__)
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# define DRM_PAGE_SIZE getpagesize()
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#else
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# define DRM_PAGE_SIZE 4096
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#endif
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#ifdef GLXEXT
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/* Initialize the visual configs that are supported by the hardware.
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* These are combined with the visual configs that the indirect
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* rendering core supports, and the intersection is exported to the
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* client.
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*/
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static Bool ATIInitVisualConfigs(ScreenPtr pScreen)
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{
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KdScreenPriv(pScreen);
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ATIScreenInfo(pScreenPriv);
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int numConfigs = 0;
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__GLXvisualConfig *pConfigs = NULL;
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ATIConfigPrivPtr pATIConfigs = NULL;
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ATIConfigPrivPtr *pATIConfigPtrs = NULL;
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int i, accum, stencil, db, use_db;
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int depth = pScreenPriv->screen->fb[0].depth;
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int bpp = pScreenPriv->screen->fb[0].bitsPerPixel;
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if (depth != 16 && (depth != 24 || bpp != 32))
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ErrorF("DRI GLX unsupported at %d/%d depth/bpp\n", depth, bpp);
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if (atis->depthOffset != 0)
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use_db = 1;
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else
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use_db = 0;
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numConfigs = 4;
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if (use_db)
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numConfigs *= 2;
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pConfigs = xcalloc(sizeof(__GLXvisualConfig), numConfigs);
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pATIConfigs = xcalloc(sizeof(ATIConfigPrivRec), numConfigs);
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pATIConfigPtrs = xcalloc(sizeof(ATIConfigPrivPtr), numConfigs);
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if (pConfigs == NULL || pATIConfigs == NULL || pATIConfigPtrs == NULL) {
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xfree(pConfigs);
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xfree(pATIConfigs);
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xfree(pATIConfigPtrs);
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return FALSE;
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}
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i = 0;
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for (db = 0; db <= use_db; db++) {
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for (accum = 0; accum <= 1; accum++) {
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for (stencil = 0; stencil <= 1; stencil++) {
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pATIConfigPtrs[i] = &pATIConfigs[i];
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pConfigs[i].vid = (VisualID)(-1);
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pConfigs[i].class = -1;
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pConfigs[i].rgba = TRUE;
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if (depth == 16) {
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pConfigs[i].redSize = 5;
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pConfigs[i].greenSize = 6;
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pConfigs[i].blueSize = 5;
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pConfigs[i].alphaSize = 0;
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pConfigs[i].redMask = 0x0000F800;
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pConfigs[i].greenMask = 0x000007E0;
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pConfigs[i].blueMask = 0x0000001F;
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pConfigs[i].alphaMask = 0x00000000;
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} else {
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pConfigs[i].redSize = 8;
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pConfigs[i].greenSize = 8;
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pConfigs[i].blueSize = 8;
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pConfigs[i].alphaSize = 8;
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pConfigs[i].redMask = 0x00FF0000;
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pConfigs[i].greenMask = 0x0000FF00;
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pConfigs[i].blueMask = 0x000000FF;
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pConfigs[i].alphaMask = 0xFF000000;
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}
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if (accum) { /* Simulated in software */
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pConfigs[i].accumRedSize = 16;
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pConfigs[i].accumGreenSize = 16;
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pConfigs[i].accumBlueSize = 16;
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if (depth == 16)
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pConfigs[i].accumAlphaSize = 0;
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else
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pConfigs[i].accumAlphaSize = 16;
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} else {
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pConfigs[i].accumRedSize = 0;
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pConfigs[i].accumGreenSize = 0;
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pConfigs[i].accumBlueSize = 0;
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pConfigs[i].accumAlphaSize = 0;
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}
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if (db)
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pConfigs[i].doubleBuffer = TRUE;
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else
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pConfigs[i].doubleBuffer = FALSE;
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pConfigs[i].stereo = FALSE;
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if (depth == 16) {
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pConfigs[i].bufferSize = 16;
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pConfigs[i].depthSize = 16;
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if (stencil)
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pConfigs[i].stencilSize = 8;
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else
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pConfigs[i].stencilSize = 0;
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} else {
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pConfigs[i].bufferSize = 32;
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if (stencil) {
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pConfigs[i].depthSize = 24;
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pConfigs[i].stencilSize = 8;
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} else {
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pConfigs[i].depthSize = 24;
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pConfigs[i].stencilSize = 0;
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}
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}
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pConfigs[i].auxBuffers = 0;
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pConfigs[i].level = 0;
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if (accum) {
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pConfigs[i].visualRating = GLX_SLOW_CONFIG;
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} else {
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pConfigs[i].visualRating = GLX_NONE;
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}
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pConfigs[i].transparentPixel = GLX_NONE;
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pConfigs[i].transparentRed = 0;
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pConfigs[i].transparentGreen = 0;
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pConfigs[i].transparentBlue = 0;
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pConfigs[i].transparentAlpha = 0;
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pConfigs[i].transparentIndex = 0;
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i++;
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}
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}
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}
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atis->numVisualConfigs = numConfigs;
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atis->pVisualConfigs = pConfigs;
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atis->pVisualConfigsPriv = pATIConfigs;
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GlxSetVisualConfigs(numConfigs, pConfigs, (void**)pATIConfigPtrs);
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return TRUE;
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}
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#endif /* GLXEXT */
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static void
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ATIDRIInitGARTValues(ScreenPtr pScreen)
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{
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KdScreenPriv(pScreen);
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ATIScreenInfo(pScreenPriv);
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int s, l;
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atis->gartOffset = 0;
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/* Initialize the ring buffer data */
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atis->ringStart = atis->gartOffset;
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atis->ringMapSize = atis->ringSize * 1024 * 1024 + DRM_PAGE_SIZE;
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atis->ringReadOffset = atis->ringStart + atis->ringMapSize;
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atis->ringReadMapSize = DRM_PAGE_SIZE;
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/* Reserve space for vertex/indirect buffers */
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atis->bufStart = atis->ringReadOffset + atis->ringReadMapSize;
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atis->bufMapSize = atis->bufSize * 1024 * 1024;
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/* Reserve the rest for GART textures */
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atis->gartTexStart = atis->bufStart + atis->bufMapSize;
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s = (atis->gartSize * 1024 * 1024 - atis->gartTexStart);
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l = ATILog2((s-1) / ATI_NR_TEX_REGIONS);
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if (l < ATI_LOG_TEX_GRANULARITY) l = ATI_LOG_TEX_GRANULARITY;
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atis->gartTexMapSize = (s >> l) << l;
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atis->log2GARTTexGran = l;
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}
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static int
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ATIDRIAddAndMap(int fd, drmHandle offset, drmSize size,
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drmMapType type, drmMapFlags flags, drmHandlePtr handle,
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drmAddressPtr address, char *desc)
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{
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char *name;
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name = (type == DRM_AGP) ? "agp" : "pci";
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if (drmAddMap(fd, offset, size, type, flags, handle) < 0) {
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ErrorF("[%s] Could not add %s mapping\n", name, desc);
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return FALSE;
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}
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ErrorF("[%s] %s handle = 0x%08lx\n", name, desc, *handle);
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if (drmMap(fd, *handle, size, address) < 0) {
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ErrorF("[%s] Could not map %s\n", name, desc);
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return FALSE;
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}
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ErrorF("[%s] %s mapped at 0x%08lx\n", name, desc, *address);
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return TRUE;
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}
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/* Initialize the AGP state. Request memory for use in AGP space, and
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initialize the Rage 128 registers to point to that memory. */
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static Bool
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ATIDRIAgpInit(ScreenPtr pScreen)
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{
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KdScreenPriv(pScreen);
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ATIScreenInfo(pScreenPriv);
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ATICardInfo(pScreenPriv);
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unsigned char *mmio = atic->reg_base;
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unsigned long mode;
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int ret;
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CARD32 cntl, chunk;
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if (drmAgpAcquire(atic->drmFd) < 0) {
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ErrorF("[agp] AGP not available\n");
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return FALSE;
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}
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ATIDRIInitGARTValues(pScreen);
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mode = drmAgpGetMode(atic->drmFd);
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if (atic->is_radeon) {
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mode &= ~RADEON_AGP_MODE_MASK;
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mode |= RADEON_AGP_1X_MODE;
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} else {
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mode &= ~R128_AGP_MODE_MASK;
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mode |= R128_AGP_1X_MODE;
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}
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if (drmAgpEnable(atic->drmFd, mode) < 0) {
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ErrorF("[agp] AGP not enabled\n");
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drmAgpRelease(atic->drmFd);
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return FALSE;
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}
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ErrorF("[agp] Mode 0x%08x selected\n", drmAgpGetMode(atic->drmFd));
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if ((ret = drmAgpAlloc(atic->drmFd, atis->gartSize * 1024 * 1024, 0,
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NULL, &atis->agpMemHandle)) < 0) {
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ErrorF("[agp] Out of memory (%d)\n", ret);
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drmAgpRelease(atic->drmFd);
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return FALSE;
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}
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ErrorF("[agp] %d kB allocated with handle 0x%08lx\n",
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atis->gartSize * 1024, (long)atis->agpMemHandle);
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if (drmAgpBind(atic->drmFd, atis->agpMemHandle, atis->gartOffset) < 0) {
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ErrorF("[agp] Could not bind\n");
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drmAgpFree(atic->drmFd, atis->agpMemHandle);
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drmAgpRelease(atic->drmFd);
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return FALSE;
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}
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if (!ATIDRIAddAndMap(atic->drmFd, atis->ringStart, atis->ringMapSize,
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DRM_AGP, DRM_READ_ONLY, &atis->ringHandle,
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(drmAddressPtr)&atis->ring, "ring"))
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return FALSE;
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if (!ATIDRIAddAndMap(atic->drmFd, atis->ringReadOffset,
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atis->ringReadMapSize, DRM_AGP, DRM_READ_ONLY,
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&atis->ringReadPtrHandle, (drmAddressPtr)&atis->ringReadPtr,
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"ring read ptr"))
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return FALSE;
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if (!ATIDRIAddAndMap(atic->drmFd, atis->bufStart, atis->bufMapSize,
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DRM_AGP, 0, &atis->bufHandle, (drmAddressPtr)&atis->buf,
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"vertex/indirect buffers"))
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return FALSE;
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if (!ATIDRIAddAndMap(atic->drmFd, atis->gartTexStart,
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atis->gartTexMapSize, DRM_AGP, 0, &atis->gartTexHandle,
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(drmAddressPtr)&atis->gartTex, "AGP texture map"))
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return FALSE;
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if (atic->is_r100) {
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/* Workaround for some hardware bugs */
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cntl = MMIO_IN32(mmio, ATI_REG_AGP_CNTL);
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MMIO_OUT32(mmio, ATI_REG_AGP_CNTL, cntl |
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RADEON_PENDING_SLOTS_VAL | RADEON_PENDING_SLOTS_SEL);
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} else if (!atic->is_radeon) {
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cntl = MMIO_IN32(mmio, ATI_REG_AGP_CNTL);
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cntl &= ~R128_AGP_APER_SIZE_MASK;
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switch (atis->gartSize) {
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case 256: cntl |= R128_AGP_APER_SIZE_256MB; break;
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case 128: cntl |= R128_AGP_APER_SIZE_128MB; break;
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case 64: cntl |= R128_AGP_APER_SIZE_64MB; break;
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case 32: cntl |= R128_AGP_APER_SIZE_32MB; break;
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case 16: cntl |= R128_AGP_APER_SIZE_16MB; break;
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case 8: cntl |= R128_AGP_APER_SIZE_8MB; break;
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case 4: cntl |= R128_AGP_APER_SIZE_4MB; break;
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default:
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ErrorF("[agp] Illegal aperture size %d kB\n", atis->gartSize *
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1024);
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return FALSE;
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}
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MMIO_OUT32(mmio, ATI_REG_AGP_CNTL, cntl);
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/* Disable Rage 128 PCIGART registers */
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chunk = MMIO_IN32(mmio, R128_REG_BM_CHUNK_0_VAL);
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chunk &= ~(R128_BM_PTR_FORCE_TO_PCI |
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R128_BM_PM4_RD_FORCE_TO_PCI |
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R128_BM_GLOBAL_FORCE_TO_PCI);
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MMIO_OUT32(mmio, R128_REG_BM_CHUNK_0_VAL, chunk);
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/* Ensure AGP GART is used (for now) */
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MMIO_OUT32(mmio, R128_REG_PCI_GART_PAGE, 1);
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}
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MMIO_OUT32(mmio, ATI_REG_AGP_BASE, drmAgpBase(atic->drmFd));
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return TRUE;
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}
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static Bool
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ATIDRIPciInit(ScreenPtr pScreen)
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{
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KdScreenPriv(pScreen);
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ATIScreenInfo(pScreenPriv);
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ATICardInfo(pScreenPriv);
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unsigned char *mmio = atic->reg_base;
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CARD32 chunk;
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int ret;
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ATIDRIInitGARTValues(pScreen);
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ret = drmScatterGatherAlloc(atic->drmFd, atis->gartSize * 1024 * 1024,
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&atis->pciMemHandle);
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if (ret < 0) {
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ErrorF("[pci] Out of memory (%d)\n", ret);
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return FALSE;
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}
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ErrorF("[pci] %d kB allocated with handle 0x%08lx\n",
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atis->gartSize * 1024, (long)atis->pciMemHandle);
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if (!ATIDRIAddAndMap(atic->drmFd, atis->ringStart, atis->ringMapSize,
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DRM_SCATTER_GATHER, DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL,
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&atis->ringHandle, (drmAddressPtr)&atis->ring, "ring"))
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return FALSE;
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if (!ATIDRIAddAndMap(atic->drmFd, atis->ringReadOffset,
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atis->ringReadMapSize, DRM_SCATTER_GATHER,
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DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL,
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&atis->ringReadPtrHandle, (drmAddressPtr)&atis->ringReadPtr,
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"ring read ptr"))
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return FALSE;
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if (!ATIDRIAddAndMap(atic->drmFd, atis->bufStart, atis->bufMapSize,
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DRM_SCATTER_GATHER, 0, &atis->bufHandle, (drmAddressPtr)&atis->buf,
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"vertex/indirect buffers"))
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return FALSE;
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if (!ATIDRIAddAndMap(atic->drmFd, atis->gartTexStart,
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atis->gartTexMapSize, DRM_SCATTER_GATHER, 0, &atis->gartTexHandle,
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(drmAddressPtr)&atis->gartTex, "PCI texture map"))
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return FALSE;
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if (!atic->is_radeon) {
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/* Force PCI GART mode */
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chunk = MMIO_IN32(mmio, R128_REG_BM_CHUNK_0_VAL);
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chunk |= (R128_BM_PTR_FORCE_TO_PCI |
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R128_BM_PM4_RD_FORCE_TO_PCI | R128_BM_GLOBAL_FORCE_TO_PCI);
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MMIO_OUT32(mmio, R128_REG_BM_CHUNK_0_VAL, chunk);
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/* Ensure PCI GART is used */
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MMIO_OUT32(mmio, R128_REG_PCI_GART_PAGE, 0);
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}
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return TRUE;
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}
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/* Initialize the kernel data structures. */
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static int
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R128DRIKernelInit(ScreenPtr pScreen)
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{
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KdScreenPriv(pScreen);
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ATIScreenInfo(pScreenPriv);
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ATICardInfo(pScreenPriv);
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drmR128Init drmInfo;
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int bpp = pScreenPriv->screen->fb[0].bitsPerPixel;
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memset(&drmInfo, 0, sizeof(drmR128Init) );
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drmInfo.func = DRM_R128_INIT_CCE;
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drmInfo.sarea_priv_offset = sizeof(XF86DRISAREARec);
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drmInfo.is_pci = !atis->using_agp;
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drmInfo.cce_mode = R128_PM4_64BM_64VCBM_64INDBM;
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drmInfo.cce_secure = TRUE;
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drmInfo.ring_size = atis->ringSize * 1024 * 1024;
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drmInfo.usec_timeout = atis->DMAusecTimeout;
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drmInfo.front_offset = atis->frontOffset;
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drmInfo.front_pitch = atis->frontPitch / (bpp / 8);
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drmInfo.back_offset = atis->backOffset;
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drmInfo.back_pitch = atis->backPitch / (bpp / 8);
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drmInfo.fb_bpp = bpp;
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drmInfo.depth_offset = atis->depthOffset;
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drmInfo.depth_pitch = atis->depthPitch / (bpp / 8);
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drmInfo.depth_bpp = bpp;
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drmInfo.span_offset = atis->spanOffset;
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drmInfo.fb_offset = atis->fbHandle;
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drmInfo.mmio_offset = atis->registerHandle;
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drmInfo.ring_offset = atis->ringHandle;
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drmInfo.ring_rptr_offset = atis->ringReadPtrHandle;
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drmInfo.buffers_offset = atis->bufHandle;
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drmInfo.agp_textures_offset = atis->gartTexHandle;
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if (drmCommandWrite(atic->drmFd, DRM_R128_INIT, &drmInfo,
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sizeof(drmR128Init)) < 0)
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return FALSE;
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return TRUE;
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}
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|
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/* Initialize the kernel data structures */
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static int
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RadeonDRIKernelInit(ScreenPtr pScreen)
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{
|
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KdScreenPriv(pScreen);
|
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ATIScreenInfo(pScreenPriv);
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ATICardInfo(pScreenPriv);
|
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drmRadeonInit drmInfo;
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|
|
|
memset(&drmInfo, 0, sizeof(drmRadeonInit));
|
|
|
|
if (atic->is_r200)
|
|
drmInfo.func = DRM_RADEON_INIT_R200_CP;
|
|
else
|
|
drmInfo.func = DRM_RADEON_INIT_CP;
|
|
|
|
drmInfo.sarea_priv_offset = sizeof(XF86DRISAREARec);
|
|
drmInfo.is_pci = !atis->using_agp;
|
|
drmInfo.cp_mode = RADEON_CSQ_PRIBM_INDBM;
|
|
drmInfo.gart_size = atis->gartSize * 1024 * 1024;
|
|
drmInfo.ring_size = atis->ringSize * 1024 * 1024;
|
|
drmInfo.usec_timeout = atis->DMAusecTimeout;
|
|
|
|
drmInfo.front_offset = atis->frontOffset;
|
|
drmInfo.front_pitch = atis->frontPitch;
|
|
drmInfo.back_offset = atis->backOffset;
|
|
drmInfo.back_pitch = atis->backPitch;
|
|
drmInfo.fb_bpp = pScreenPriv->screen->fb[0].bitsPerPixel;
|
|
drmInfo.depth_offset = atis->depthOffset;
|
|
drmInfo.depth_pitch = atis->depthPitch;
|
|
drmInfo.depth_bpp = pScreenPriv->screen->fb[0].bitsPerPixel;
|
|
|
|
drmInfo.fb_offset = atis->fbHandle;
|
|
drmInfo.mmio_offset = atis->registerHandle;
|
|
drmInfo.ring_offset = atis->ringHandle;
|
|
drmInfo.ring_rptr_offset = atis->ringReadPtrHandle;
|
|
drmInfo.buffers_offset = atis->bufHandle;
|
|
drmInfo.gart_textures_offset = atis->gartTexHandle;
|
|
|
|
if (drmCommandWrite(atic->drmFd, DRM_RADEON_CP_INIT,
|
|
&drmInfo, sizeof(drmRadeonInit)) < 0)
|
|
return FALSE;
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
/* Add a map for the vertex buffers that will be accessed by any
|
|
DRI-based clients. */
|
|
static Bool
|
|
ATIDRIBufInit(ScreenPtr pScreen)
|
|
{
|
|
KdScreenPriv(pScreen);
|
|
ATIScreenInfo(pScreenPriv);
|
|
ATICardInfo(pScreenPriv);
|
|
int type, size;
|
|
|
|
if (atic->is_radeon)
|
|
size = RADEON_BUFFER_SIZE;
|
|
else
|
|
size = R128_BUFFER_SIZE;
|
|
|
|
if (atis->using_agp)
|
|
type = DRM_AGP_BUFFER;
|
|
else
|
|
type = DRM_SG_BUFFER;
|
|
|
|
/* Initialize vertex buffers */
|
|
atis->bufNumBufs = drmAddBufs(atic->drmFd, atis->bufMapSize / size,
|
|
size, type, atis->bufStart);
|
|
|
|
if (atis->bufNumBufs <= 0) {
|
|
ErrorF("[drm] Could not create vertex/indirect buffers list\n");
|
|
return FALSE;
|
|
}
|
|
ErrorF("[drm] Added %d %d byte vertex/indirect buffers\n",
|
|
atis->bufNumBufs, size);
|
|
|
|
atis->buffers = drmMapBufs(atic->drmFd);
|
|
if (atis->buffers == NULL) {
|
|
ErrorF("[drm] Failed to map vertex/indirect buffers list\n");
|
|
return FALSE;
|
|
}
|
|
ErrorF("[drm] Mapped %d vertex/indirect buffers\n",
|
|
atis->buffers->count);
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
static int
|
|
ATIDRIIrqInit(ScreenPtr pScreen)
|
|
{
|
|
KdScreenPriv(pScreen);
|
|
ATIScreenInfo(pScreenPriv);
|
|
ATICardInfo(pScreenPriv);
|
|
|
|
if (atis->irqEnabled)
|
|
return FALSE;
|
|
|
|
atis->irqEnabled = drmCtlInstHandler(atic->drmFd, 0);
|
|
|
|
if (!atis->irqEnabled)
|
|
return FALSE;
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
static void ATIDRISwapContext(ScreenPtr pScreen, DRISyncType syncType,
|
|
DRIContextType oldContextType, void *oldContext,
|
|
DRIContextType newContextType, void *newContext)
|
|
{
|
|
KdScreenPriv(pScreen);
|
|
ATIScreenInfo(pScreenPriv);
|
|
|
|
if ((syncType==DRI_3D_SYNC) && (oldContextType==DRI_2D_CONTEXT) &&
|
|
(newContextType==DRI_2D_CONTEXT)) {
|
|
/* Entering from Wakeup */
|
|
KdMarkSync(pScreen);
|
|
}
|
|
if ((syncType==DRI_2D_SYNC) && (oldContextType==DRI_NO_CONTEXT) &&
|
|
(newContextType==DRI_2D_CONTEXT)) {
|
|
/* Exiting from Block Handler */
|
|
if (atis->dma_started)
|
|
ATIFlushIndirect(atis, 1);
|
|
}
|
|
}
|
|
|
|
static Bool ATIDRIFinishScreenInit(ScreenPtr pScreen);
|
|
|
|
/* Initialize the screen-specific data structures for the Radeon or
|
|
Rage 128. This is the main entry point to the device-specific
|
|
initialization code. It calls device-independent DRI functions to
|
|
create the DRI data structures and initialize the DRI state. */
|
|
Bool
|
|
ATIDRIScreenInit(ScreenPtr pScreen)
|
|
{
|
|
KdScreenPriv(pScreen);
|
|
ATIScreenInfo(pScreenPriv);
|
|
ATICardInfo(pScreenPriv);
|
|
void *scratch_ptr;
|
|
int scratch_int;
|
|
DRIInfoPtr pDRIInfo;
|
|
int devSareaSize;
|
|
drmSetVersion sv;
|
|
|
|
if (pScreenPriv->screen->fb[0].depth < 16 ||
|
|
pScreenPriv->screen->fb[0].bitsPerPixel == 24) {
|
|
ErrorF("DRI unsupported at this depth/bpp, disabling.\n");
|
|
return FALSE;
|
|
}
|
|
|
|
atis->agpMode = 1;
|
|
atis->gartSize = 8;
|
|
atis->ringSize = 1;
|
|
atis->bufSize = 2;
|
|
atis->gartTexSize = 1;
|
|
atis->DMAusecTimeout = 10000;
|
|
|
|
if (atic->drmFd < 0)
|
|
return FALSE;
|
|
|
|
sv.drm_di_major = -1;
|
|
sv.drm_dd_major = -1;
|
|
drmSetInterfaceVersion(atic->drmFd, &sv);
|
|
if (atic->is_radeon) {
|
|
if (sv.drm_dd_major != 1 || sv.drm_dd_minor < 6) {
|
|
ErrorF("[dri] radeon kernel module version is %d.%d "
|
|
"but version 1.6 or greater is needed.\n",
|
|
sv.drm_dd_major, sv.drm_dd_minor);
|
|
return FALSE;
|
|
}
|
|
} else {
|
|
if (sv.drm_dd_major != 2 || sv.drm_dd_minor < 2) {
|
|
ErrorF("[dri] r128 kernel module version is %d.%d "
|
|
"but version 2.2 or greater is needed.\n",
|
|
sv.drm_dd_major, sv.drm_dd_minor);
|
|
return FALSE;
|
|
}
|
|
}
|
|
|
|
/* Create the DRI data structure, and fill it in before calling the
|
|
* DRIScreenInit().
|
|
*/
|
|
pDRIInfo = DRICreateInfoRec();
|
|
if (pDRIInfo == NULL)
|
|
return FALSE;
|
|
|
|
atis->pDRIInfo = pDRIInfo;
|
|
pDRIInfo->busIdString = atic->busid;
|
|
if (atic->is_radeon) {
|
|
pDRIInfo->drmDriverName = "radeon";
|
|
if (atic->is_r100)
|
|
pDRIInfo->clientDriverName = "radeon";
|
|
else
|
|
pDRIInfo->clientDriverName = "r200";
|
|
} else {
|
|
pDRIInfo->drmDriverName = "r128";
|
|
pDRIInfo->clientDriverName = "r128";
|
|
}
|
|
pDRIInfo->ddxDriverMajorVersion = 4;
|
|
pDRIInfo->ddxDriverMinorVersion = 0;
|
|
pDRIInfo->ddxDriverPatchVersion = 0;
|
|
pDRIInfo->frameBufferPhysicalAddress =
|
|
pScreenPriv->card->attr.address[0] & 0xfc000000;
|
|
pDRIInfo->frameBufferSize = pScreenPriv->screen->memory_size;
|
|
pDRIInfo->frameBufferStride = pScreenPriv->screen->fb[0].byteStride;
|
|
pDRIInfo->ddxDrawableTableEntry = SAREA_MAX_DRAWABLES;
|
|
pDRIInfo->maxDrawableTableEntry = SAREA_MAX_DRAWABLES;
|
|
|
|
/* For now the mapping works by using a fixed size defined
|
|
* in the SAREA header
|
|
*/
|
|
pDRIInfo->SAREASize = SAREA_MAX;
|
|
|
|
if (atic->is_radeon) {
|
|
pDRIInfo->devPrivateSize = sizeof(RADEONDRIRec);
|
|
devSareaSize = sizeof(RADEONSAREAPriv);
|
|
} else {
|
|
pDRIInfo->devPrivateSize = sizeof(R128DRIRec);
|
|
devSareaSize = sizeof(R128SAREAPriv);
|
|
}
|
|
|
|
if (sizeof(XF86DRISAREARec) + devSareaSize > SAREA_MAX) {
|
|
ErrorF("[dri] Data does not fit in SAREA. Disabling DRI.\n");
|
|
return FALSE;
|
|
}
|
|
|
|
pDRIInfo->devPrivate = xcalloc(pDRIInfo->devPrivateSize, 1);
|
|
if (pDRIInfo->devPrivate == NULL) {
|
|
DRIDestroyInfoRec(atis->pDRIInfo);
|
|
atis->pDRIInfo = NULL;
|
|
return FALSE;
|
|
}
|
|
|
|
pDRIInfo->contextSize = sizeof(ATIDRIContextRec);
|
|
|
|
pDRIInfo->SwapContext = ATIDRISwapContext;
|
|
/*pDRIInfo->InitBuffers = R128DRIInitBuffers;*/ /* XXX Appears unnecessary */
|
|
/*pDRIInfo->MoveBuffers = R128DRIMoveBuffers;*/ /* XXX Badness */
|
|
pDRIInfo->bufferRequests = DRI_ALL_WINDOWS;
|
|
/*pDRIInfo->TransitionTo2d = R128DRITransitionTo2d;
|
|
pDRIInfo->TransitionTo3d = R128DRITransitionTo3d;
|
|
pDRIInfo->TransitionSingleToMulti3D = R128DRITransitionSingleToMulti3d;
|
|
pDRIInfo->TransitionMultiToSingle3D = R128DRITransitionMultiToSingle3d;*/
|
|
|
|
pDRIInfo->createDummyCtx = TRUE;
|
|
pDRIInfo->createDummyCtxPriv = FALSE;
|
|
|
|
if (!DRIScreenInit(pScreen, pDRIInfo, &atic->drmFd)) {
|
|
ErrorF("[dri] DRIScreenInit failed. Disabling DRI.\n");
|
|
xfree(pDRIInfo->devPrivate);
|
|
pDRIInfo->devPrivate = NULL;
|
|
DRIDestroyInfoRec(pDRIInfo);
|
|
pDRIInfo = NULL;
|
|
return FALSE;
|
|
}
|
|
|
|
/* Add a map for the MMIO registers that will be accessed by any
|
|
* DRI-based clients.
|
|
*/
|
|
atis->registerSize = ATI_REG_SIZE(pScreenPriv->screen->card);
|
|
if (drmAddMap(atic->drmFd, ATI_REG_BASE(pScreenPriv->screen->card),
|
|
atis->registerSize, DRM_REGISTERS, DRM_READ_ONLY,
|
|
&atis->registerHandle) < 0) {
|
|
ATIDRICloseScreen(pScreen);
|
|
return FALSE;
|
|
}
|
|
ErrorF("[drm] register handle = 0x%08lx\n", atis->registerHandle);
|
|
|
|
/* DRIScreenInit adds the frame buffer map, but we need it as well */
|
|
DRIGetDeviceInfo(pScreen, &atis->fbHandle, &scratch_int, &scratch_int,
|
|
&scratch_int, &scratch_int, &scratch_ptr);
|
|
|
|
/* Initialize AGP */
|
|
atis->using_agp = atic->is_agp;
|
|
if (atic->is_agp && !ATIDRIAgpInit(pScreen)) {
|
|
atis->using_agp = FALSE;
|
|
ErrorF("[agp] AGP failed to initialize; falling back to PCI mode.\n");
|
|
ErrorF("[agp] Make sure your kernel's AGP support is loaded and functioning.\n");
|
|
}
|
|
|
|
/* Initialize PCIGART */
|
|
if (!atis->using_agp && !ATIDRIPciInit(pScreen)) {
|
|
ATIDRICloseScreen(pScreen);
|
|
return FALSE;
|
|
}
|
|
|
|
#ifdef GLXEXT
|
|
if (!ATIInitVisualConfigs(pScreen)) {
|
|
ATIDRICloseScreen(pScreen);
|
|
return FALSE;
|
|
}
|
|
ErrorF("[dri] Visual configs initialized\n");
|
|
#endif
|
|
|
|
atis->serverContext = DRIGetContext(pScreen);
|
|
|
|
return ATIDRIFinishScreenInit(pScreen);
|
|
}
|
|
|
|
/* Finish initializing the device-dependent DRI state, and call
|
|
DRIFinishScreenInit() to complete the device-independent DRI
|
|
initialization. */
|
|
static Bool
|
|
R128DRIFinishScreenInit(ScreenPtr pScreen)
|
|
{
|
|
KdScreenPriv(pScreen);
|
|
ATIScreenInfo(pScreenPriv);
|
|
R128SAREAPrivPtr pSAREAPriv;
|
|
R128DRIPtr pR128DRI;
|
|
int bpp = pScreenPriv->screen->fb[0].bitsPerPixel;
|
|
|
|
/* Initialize the kernel data structures */
|
|
if (!R128DRIKernelInit(pScreen)) {
|
|
ATIDRICloseScreen(pScreen);
|
|
return FALSE;
|
|
}
|
|
|
|
/* Initialize the vertex buffers list */
|
|
if (!ATIDRIBufInit(pScreen)) {
|
|
ATIDRICloseScreen(pScreen);
|
|
return FALSE;
|
|
}
|
|
|
|
/* Initialize IRQ */
|
|
ATIDRIIrqInit(pScreen);
|
|
|
|
pSAREAPriv = (R128SAREAPrivPtr)DRIGetSAREAPrivate(pScreen);
|
|
memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
|
|
|
|
pR128DRI = (R128DRIPtr)atis->pDRIInfo->devPrivate;
|
|
|
|
pR128DRI->deviceID = pScreenPriv->screen->card->attr.deviceID;
|
|
pR128DRI->width = pScreenPriv->screen->width;
|
|
pR128DRI->height = pScreenPriv->screen->height;
|
|
pR128DRI->depth = pScreenPriv->screen->fb[0].depth;
|
|
pR128DRI->bpp = pScreenPriv->screen->fb[0].bitsPerPixel;
|
|
|
|
pR128DRI->IsPCI = !atis->using_agp;
|
|
pR128DRI->AGPMode = atis->agpMode;
|
|
|
|
pR128DRI->frontOffset = atis->frontOffset;
|
|
pR128DRI->frontPitch = atis->frontPitch / (bpp / 8);
|
|
pR128DRI->backOffset = atis->backOffset;
|
|
pR128DRI->backPitch = atis->backPitch / (bpp / 8);
|
|
pR128DRI->depthOffset = atis->depthOffset;
|
|
pR128DRI->depthPitch = atis->depthPitch / (bpp / 8);
|
|
pR128DRI->spanOffset = atis->spanOffset;
|
|
pR128DRI->textureOffset = atis->textureOffset;
|
|
pR128DRI->textureSize = atis->textureSize;
|
|
pR128DRI->log2TexGran = atis->log2TexGran;
|
|
|
|
pR128DRI->registerHandle = atis->registerHandle;
|
|
pR128DRI->registerSize = atis->registerSize;
|
|
|
|
pR128DRI->gartTexHandle = atis->gartTexHandle;
|
|
pR128DRI->gartTexMapSize = atis->gartTexMapSize;
|
|
pR128DRI->log2AGPTexGran = atis->log2GARTTexGran;
|
|
pR128DRI->gartTexOffset = atis->gartTexStart;
|
|
pR128DRI->sarea_priv_offset = sizeof(XF86DRISAREARec);
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
/* Finish initializing the device-dependent DRI state, and call
|
|
* DRIFinishScreenInit() to complete the device-independent DRI
|
|
* initialization.
|
|
*/
|
|
static Bool
|
|
RadeonDRIFinishScreenInit(ScreenPtr pScreen)
|
|
{
|
|
KdScreenPriv(pScreen);
|
|
ATIScreenInfo(pScreenPriv);
|
|
ATICardInfo(pScreenPriv);
|
|
RADEONSAREAPrivPtr pSAREAPriv;
|
|
RADEONDRIPtr pRADEONDRI;
|
|
drmRadeonMemInitHeap drmHeap;
|
|
|
|
/* Initialize the kernel data structures */
|
|
if (!RadeonDRIKernelInit(pScreen)) {
|
|
ATIDRICloseScreen(pScreen);
|
|
return FALSE;
|
|
}
|
|
|
|
/* Initialize the vertex buffers list */
|
|
if (!ATIDRIBufInit(pScreen)) {
|
|
ATIDRICloseScreen(pScreen);
|
|
return FALSE;
|
|
}
|
|
|
|
/* Initialize IRQ */
|
|
ATIDRIIrqInit(pScreen);
|
|
|
|
drmHeap.region = RADEON_MEM_REGION_GART;
|
|
drmHeap.start = 0;
|
|
drmHeap.size = atis->gartTexMapSize;
|
|
|
|
if (drmCommandWrite(atic->drmFd, DRM_RADEON_INIT_HEAP, &drmHeap,
|
|
sizeof(drmHeap))) {
|
|
ErrorF("[drm] Failed to initialize GART heap manager\n");
|
|
}
|
|
|
|
/* Initialize the SAREA private data structure */
|
|
pSAREAPriv = (RADEONSAREAPrivPtr)DRIGetSAREAPrivate(pScreen);
|
|
memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
|
|
|
|
pRADEONDRI = (RADEONDRIPtr)atis->pDRIInfo->devPrivate;
|
|
|
|
pRADEONDRI->deviceID = pScreenPriv->screen->card->attr.deviceID;
|
|
pRADEONDRI->width = pScreenPriv->screen->width;
|
|
pRADEONDRI->height = pScreenPriv->screen->height;
|
|
pRADEONDRI->depth = pScreenPriv->screen->fb[0].depth;
|
|
pRADEONDRI->bpp = pScreenPriv->screen->fb[0].bitsPerPixel;
|
|
|
|
pRADEONDRI->IsPCI = !atis->using_agp;
|
|
pRADEONDRI->AGPMode = atis->agpMode;
|
|
|
|
pRADEONDRI->frontOffset = atis->frontOffset;
|
|
pRADEONDRI->frontPitch = atis->frontPitch;
|
|
pRADEONDRI->backOffset = atis->backOffset;
|
|
pRADEONDRI->backPitch = atis->backPitch;
|
|
pRADEONDRI->depthOffset = atis->depthOffset;
|
|
pRADEONDRI->depthPitch = atis->depthPitch;
|
|
pRADEONDRI->textureOffset = atis->textureOffset;
|
|
pRADEONDRI->textureSize = atis->textureSize;
|
|
pRADEONDRI->log2TexGran = atis->log2TexGran;
|
|
|
|
pRADEONDRI->registerHandle = atis->registerHandle;
|
|
pRADEONDRI->registerSize = atis->registerSize;
|
|
|
|
pRADEONDRI->statusHandle = atis->ringReadPtrHandle;
|
|
pRADEONDRI->statusSize = atis->ringReadMapSize;
|
|
|
|
pRADEONDRI->gartTexHandle = atis->gartTexHandle;
|
|
pRADEONDRI->gartTexMapSize = atis->gartTexMapSize;
|
|
pRADEONDRI->log2GARTTexGran = atis->log2GARTTexGran;
|
|
pRADEONDRI->gartTexOffset = atis->gartTexStart;
|
|
|
|
pRADEONDRI->sarea_priv_offset = sizeof(XF86DRISAREARec);
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
static Bool
|
|
ATIDRIFinishScreenInit(ScreenPtr pScreen)
|
|
{
|
|
KdScreenPriv(pScreen);
|
|
ATIScreenInfo(pScreenPriv);
|
|
ATICardInfo (pScreenPriv);
|
|
|
|
atis->pDRIInfo->driverSwapMethod = DRI_HIDE_X_CONTEXT;
|
|
|
|
/* NOTE: DRIFinishScreenInit must be called before *DRIKernelInit
|
|
* because *DRIKernelInit requires that the hardware lock is held by
|
|
* the X server, and the first time the hardware lock is grabbed is
|
|
* in DRIFinishScreenInit.
|
|
*/
|
|
if (!DRIFinishScreenInit(pScreen)) {
|
|
ATIDRICloseScreen(pScreen);
|
|
return FALSE;
|
|
}
|
|
|
|
if (atic->is_radeon) {
|
|
if (!RadeonDRIFinishScreenInit(pScreen)) {
|
|
ATIDRICloseScreen(pScreen);
|
|
return FALSE;
|
|
}
|
|
} else {
|
|
if (!R128DRIFinishScreenInit(pScreen)) {
|
|
ATIDRICloseScreen(pScreen);
|
|
return FALSE;
|
|
}
|
|
}
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
/* The screen is being closed, so clean up any state and free any
|
|
resources used by the DRI. */
|
|
void
|
|
ATIDRICloseScreen(ScreenPtr pScreen)
|
|
{
|
|
KdScreenPriv (pScreen);
|
|
ATIScreenInfo (pScreenPriv);
|
|
ATICardInfo (pScreenPriv);
|
|
drmR128Init drmR128Info;
|
|
drmRadeonInit drmRadeonInfo;
|
|
|
|
if (atis->indirectBuffer != NULL) {
|
|
/* Flush any remaining commands and free indirect buffers.
|
|
* Two steps are used because ATIFlushIndirect gets a
|
|
* new buffer after discarding.
|
|
*/
|
|
ATIFlushIndirect(atis, 1);
|
|
ATIDRIDispatchIndirect(atis, 1);
|
|
xfree(atis->indirectBuffer);
|
|
atis->indirectBuffer = NULL;
|
|
atis->indirectStart = 0;
|
|
}
|
|
ATIDRIDMAStop(atis);
|
|
|
|
if (atis->irqEnabled) {
|
|
drmCtlUninstHandler(atic->drmFd);
|
|
atis->irqEnabled = FALSE;
|
|
}
|
|
|
|
/* De-allocate vertex buffers */
|
|
if (atis->buffers) {
|
|
drmUnmapBufs(atis->buffers);
|
|
atis->buffers = NULL;
|
|
}
|
|
|
|
/* De-allocate all kernel resources */
|
|
if (!atic->is_radeon) {
|
|
memset(&drmR128Info, 0, sizeof(drmR128Init));
|
|
drmR128Info.func = DRM_R128_CLEANUP_CCE;
|
|
drmCommandWrite(atic->drmFd, DRM_R128_INIT, &drmR128Info,
|
|
sizeof(drmR128Init));
|
|
} else {
|
|
memset(&drmRadeonInfo, 0, sizeof(drmRadeonInfo));
|
|
drmRadeonInfo.func = DRM_RADEON_CLEANUP_CP;
|
|
drmCommandWrite(atic->drmFd, DRM_RADEON_CP_INIT, &drmRadeonInfo,
|
|
sizeof(drmR128Init));
|
|
}
|
|
|
|
/* De-allocate all AGP resources */
|
|
if (atis->gartTex) {
|
|
drmUnmap(atis->gartTex, atis->gartTexMapSize);
|
|
atis->gartTex = NULL;
|
|
}
|
|
if (atis->buf) {
|
|
drmUnmap(atis->buf, atis->bufMapSize);
|
|
atis->buf = NULL;
|
|
}
|
|
if (atis->ringReadPtr) {
|
|
drmUnmap(atis->ringReadPtr, atis->ringReadMapSize);
|
|
atis->ringReadPtr = NULL;
|
|
}
|
|
if (atis->ring) {
|
|
drmUnmap(atis->ring, atis->ringMapSize);
|
|
atis->ring = NULL;
|
|
}
|
|
if (atis->agpMemHandle != DRM_AGP_NO_HANDLE) {
|
|
drmAgpUnbind(atic->drmFd, atis->agpMemHandle);
|
|
drmAgpFree(atic->drmFd, atis->agpMemHandle);
|
|
atis->agpMemHandle = DRM_AGP_NO_HANDLE;
|
|
drmAgpRelease(atic->drmFd);
|
|
}
|
|
if (atis->pciMemHandle) {
|
|
drmScatterGatherFree(atic->drmFd, atis->pciMemHandle);
|
|
atis->pciMemHandle = 0;
|
|
}
|
|
|
|
/* De-allocate all DRI resources */
|
|
DRICloseScreen(pScreen);
|
|
|
|
/* De-allocate all DRI data structures */
|
|
if (atis->pDRIInfo) {
|
|
if (atis->pDRIInfo->devPrivate) {
|
|
xfree(atis->pDRIInfo->devPrivate);
|
|
atis->pDRIInfo->devPrivate = NULL;
|
|
}
|
|
DRIDestroyInfoRec(atis->pDRIInfo);
|
|
atis->pDRIInfo = NULL;
|
|
}
|
|
|
|
#ifdef GLXEXT
|
|
if (atis->pVisualConfigs) {
|
|
xfree(atis->pVisualConfigs);
|
|
atis->pVisualConfigs = NULL;
|
|
}
|
|
if (atis->pVisualConfigsPriv) {
|
|
xfree(atis->pVisualConfigsPriv);
|
|
atis->pVisualConfigsPriv = NULL;
|
|
}
|
|
#endif /* GLXEXT */
|
|
atic->drmFd = -1;
|
|
}
|
|
|
|
void
|
|
ATIDRIDMAStart(ATIScreenInfo *atis)
|
|
{
|
|
ATICardInfo *atic = atis->atic;
|
|
int ret;
|
|
|
|
if (atic->is_radeon)
|
|
ret = drmCommandNone(atic->drmFd, DRM_RADEON_CP_START);
|
|
else
|
|
ret = drmCommandNone(atic->drmFd, DRM_R128_CCE_START);
|
|
|
|
if (ret == 0)
|
|
atis->dma_started = TRUE;
|
|
else
|
|
FatalError("%s: DMA start returned %d\n", __FUNCTION__, ret);
|
|
}
|
|
|
|
/* Attempts to idle the DMA engine and stops it. Note that the ioctl is the
|
|
* same for both R128 and Radeon, so we can just use the name of one of them.
|
|
*/
|
|
void
|
|
ATIDRIDMAStop(ATIScreenInfo *atis)
|
|
{
|
|
ATICardInfo *atic = atis->atic;
|
|
drmRadeonCPStop stop;
|
|
int ret;
|
|
|
|
stop.flush = 1;
|
|
stop.idle = 1;
|
|
ret = drmCommandWrite(atic->drmFd, DRM_RADEON_CP_STOP, &stop,
|
|
sizeof(drmRadeonCPStop));
|
|
|
|
if (ret != 0 && errno == EBUSY) {
|
|
ErrorF("Failed to idle the DMA engine\n");
|
|
|
|
stop.idle = 0;
|
|
ret = drmCommandWrite(atic->drmFd, DRM_RADEON_CP_STOP, &stop,
|
|
sizeof(drmRadeonCPStop));
|
|
}
|
|
atis->dma_started = FALSE;
|
|
}
|
|
|
|
void
|
|
ATIDRIDMAReset(ATIScreenInfo *atis)
|
|
{
|
|
ATICardInfo *atic = atis->atic;
|
|
int ret;
|
|
|
|
ret = drmCommandNone(atic->drmFd, atic->is_radeon ?
|
|
DRM_RADEON_CP_RESET : DRM_R128_CCE_RESET);
|
|
|
|
if (ret != 0)
|
|
FatalError("Failed to reset CCE/CP\n");
|
|
|
|
atis->dma_started = FALSE;
|
|
}
|
|
|
|
/* The R128 and Radeon Indirect ioctls differ only in the ioctl number */
|
|
void
|
|
ATIDRIDispatchIndirect(ATIScreenInfo *atis, Bool discard)
|
|
{
|
|
ATICardInfo *atic = atis->atic;
|
|
drmBufPtr buffer = atis->indirectBuffer->drmBuf;
|
|
drmR128Indirect indirect;
|
|
int cmd;
|
|
|
|
indirect.idx = buffer->idx;
|
|
indirect.start = atis->indirectStart;
|
|
indirect.end = buffer->used;
|
|
indirect.discard = discard;
|
|
cmd = atic->is_radeon ? DRM_RADEON_INDIRECT : DRM_R128_INDIRECT;
|
|
drmCommandWriteRead(atic->drmFd, cmd, &indirect,
|
|
sizeof(drmR128Indirect));
|
|
}
|
|
|
|
/* Get an indirect buffer for the DMA 2D acceleration commands */
|
|
drmBufPtr
|
|
ATIDRIGetBuffer(ATIScreenInfo *atis)
|
|
{
|
|
ATICardInfo *atic = atis->atic;
|
|
drmDMAReq dma;
|
|
drmBufPtr buf = NULL;
|
|
int indx = 0;
|
|
int size = 0;
|
|
int ret, tries;
|
|
|
|
dma.context = atis->serverContext;
|
|
dma.send_count = 0;
|
|
dma.send_list = NULL;
|
|
dma.send_sizes = NULL;
|
|
dma.flags = 0;
|
|
dma.request_count = 1;
|
|
if (atic->is_radeon)
|
|
dma.request_size = RADEON_BUFFER_SIZE;
|
|
else
|
|
dma.request_size = R128_BUFFER_SIZE;
|
|
dma.request_list = &indx;
|
|
dma.request_sizes = &size;
|
|
dma.granted_count = 0;
|
|
|
|
for (tries = 100; tries != 0; tries--) {
|
|
ret = drmDMA(atic->drmFd, &dma);
|
|
if (ret != -EBUSY)
|
|
break;
|
|
}
|
|
if (tries == 0)
|
|
FatalError("Timeout fetching DMA buffer (card hung)\n");
|
|
if (ret != 0)
|
|
FatalError("Error fetching DMA buffer: %d\n", ret);
|
|
|
|
buf = &atis->buffers->list[indx];
|
|
buf->used = 0;
|
|
return buf;
|
|
}
|