d23c46dd3e
permissions when no access to HW registers is required. For API changes
which mostly involve the modifications to make the RRFunc (introduced
with 6.8) more flexible please check Bugzilla #2407. NOTE: This patch
applies changes to OS specific files for other OSes which I cannot
test.
701 lines
21 KiB
C
701 lines
21 KiB
C
/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/ix86Pci.c,v 1.25 2003/09/24 02:43:34 dawes Exp $ */
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/*
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* ix86Pci.c - x86 PCI driver
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*
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* The XFree86 server PCI access functions have been reimplemented as a
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* framework that allows each supported platform/OS to have their own
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* platform/OS specific PCI driver.
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*
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* Most of the code of these functions was simply lifted from the
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* Intel architecture specifric portion of the original Xfree86
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* PCI code in hw/xfree86/common_hw/xf86_PCI.C...
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*
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* Gary Barton
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* Concurrent Computer Corporation
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* garyb@gate.net
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*/
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/*
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* Copyright 1998 by Concurrent Computer Corporation
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*
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* Permission to use, copy, modify, distribute, and sell this software
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* and its documentation for any purpose is hereby granted without fee,
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* provided that the above copyright notice appear in all copies and that
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* both that copyright notice and this permission notice appear in
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* supporting documentation, and that the name of Concurrent Computer
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* Corporation not be used in advertising or publicity pertaining to
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* distribution of the software without specific, written prior
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* permission. Concurrent Computer Corporation makes no representations
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* about the suitability of this software for any purpose. It is
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* provided "as is" without express or implied warranty.
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*
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* CONCURRENT COMPUTER CORPORATION DISCLAIMS ALL WARRANTIES WITH REGARD
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* TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS, IN NO EVENT SHALL CONCURRENT COMPUTER CORPORATION BE
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* LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
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* DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
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* WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
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* ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
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* SOFTWARE.
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*
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* Copyright 1998 by Metro Link Incorporated
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*
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* Permission to use, copy, modify, distribute, and sell this software
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* and its documentation for any purpose is hereby granted without fee,
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* provided that the above copyright notice appear in all copies and that
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* both that copyright notice and this permission notice appear in
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* supporting documentation, and that the name of Metro Link
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* Incorporated not be used in advertising or publicity pertaining to
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* distribution of the software without specific, written prior
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* permission. Metro Link Incorporated makes no representations
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* about the suitability of this software for any purpose. It is
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* provided "as is" without express or implied warranty.
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*
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* METRO LINK INCORPORATED DISCLAIMS ALL WARRANTIES WITH REGARD
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* TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS, IN NO EVENT SHALL METRO LINK INCORPORATED BE
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* LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
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* DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
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* WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
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* ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
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* SOFTWARE.
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*
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* This software is derived from the original XFree86 PCI code
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* which includes the following copyright notices as well:
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*
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* Copyright 1995 by Robin Cutshaw <robin@XFree86.Org>
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that
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* copyright notice and this permission notice appear in supporting
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* documentation, and that the names of the above listed copyright holder(s)
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* not be used in advertising or publicity pertaining to distribution of
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* the software without specific, written prior permission. The above listed
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* copyright holder(s) make(s) no representations about the suitability of this
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* software for any purpose. It is provided "as is" without express or
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* implied warranty.
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*
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* THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM(S) ALL WARRANTIES WITH REGARD
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* TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE
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* LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
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* DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER
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* IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
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* OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* This code is also based heavily on the code in FreeBSD-current, which was
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* written by Wolfgang Stanglmeier, and contains the following copyright:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1999-2003 by The XFree86 Project, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of the copyright holder(s)
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* and author(s) shall not be used in advertising or otherwise to promote
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* the sale, use or other dealings in this Software without prior written
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* authorization from the copyright holder(s) and author(s).
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*/
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#include <stdio.h>
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#include "compiler.h"
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#include "xf86.h"
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#include "xf86Priv.h"
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#include "xf86_OSlib.h"
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#include "Pci.h"
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#ifdef PC98
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#define outb(port,data) _outb(port,data)
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#define outl(port,data) _outl(port,data)
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#define inb(port) _inb(port)
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#define inl(port) _inl(port)
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#endif
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#define PCI_CFGMECH2_ENABLE_REG 0xCF8
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#ifdef PC98
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#define PCI_CFGMECH2_FORWARD_REG 0xCF9
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#else
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#define PCI_CFGMECH2_FORWARD_REG 0xCFA
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#endif
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#define PCI_CFGMECH2_MAXDEV 16
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#define PCI_ADDR_FROM_TAG_CFG1(tag,reg) (PCI_EN | tag | (reg & 0xfc))
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#define PCI_FORWARD_FROM_TAG(tag) PCI_BUS_FROM_TAG(tag)
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#define PCI_ENABLE_FROM_TAG(tag) (0xf0 | (((tag) & 0x00000700) >> 7))
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#define PCI_ADDR_FROM_TAG_CFG2(tag,reg) (0xc000 | (((tag) & 0x0000f800) >> 3) \
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| (reg & 0xfc))
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/*
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* Intel x86 platform specific PCI access functions
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*/
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static CARD32 ix86PciReadLongSetup(PCITAG tag, int off);
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static void ix86PciWriteLongSetup(PCITAG, int off, CARD32 val);
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static void ix86PciSetBitsLongSetup(PCITAG, int off, CARD32 mask, CARD32 val);
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static CARD32 ix86PciReadLongCFG1(PCITAG tag, int off);
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static void ix86PciWriteLongCFG1(PCITAG, int off, CARD32 val);
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static void ix86PciSetBitsLongCFG1(PCITAG, int off, CARD32 mask, CARD32 val);
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static CARD32 ix86PciReadLongCFG2(PCITAG tag, int off);
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static void ix86PciWriteLongCFG2(PCITAG, int off, CARD32 val);
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static void ix86PciSetBitsLongCFG2(PCITAG, int off, CARD32 mask, CARD32 val);
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static pciBusFuncs_t ix86Funcs0 = {
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/* pciReadLong */ ix86PciReadLongSetup,
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/* pciWriteLong */ ix86PciWriteLongSetup,
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/* pciSetBitsLong */ ix86PciSetBitsLongSetup,
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/* pciAddrHostToBus */ pciAddrNOOP,
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/* pciAddrBusToHost */ pciAddrNOOP
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};
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static pciBusFuncs_t ix86Funcs1 = {
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/* pciReadLong */ ix86PciReadLongCFG1,
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/* pciWriteLong */ ix86PciWriteLongCFG1,
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/* pciSetBitsLong */ ix86PciSetBitsLongCFG1,
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/* pciAddrHostToBus */ pciAddrNOOP,
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/* pciAddrBusToHost */ pciAddrNOOP
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};
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static pciBusFuncs_t ix86Funcs2 = {
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/* pciReadLong */ ix86PciReadLongCFG2,
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/* pciWriteLong */ ix86PciWriteLongCFG2,
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/* pciSetBitsLong */ ix86PciSetBitsLongCFG2,
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/* pciAddrHostToBus */ pciAddrNOOP,
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/* pciAddrBusToHost */ pciAddrNOOP
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};
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static pciBusInfo_t ix86Pci0 = {
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/* configMech */ PCI_CFG_MECH_UNKNOWN, /* Set by ix86PciInit() */
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/* numDevices */ 0, /* Set by ix86PciInit() */
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/* secondary */ FALSE,
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/* primary_bus */ 0,
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#ifdef PowerMAX_OS
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/* ppc_io_base */ 0,
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/* ppc_io_size */ 0,
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#endif
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/* funcs */ &ix86Funcs0, /* Set by ix86PciInit() */
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/* pciBusPriv */ NULL,
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/* bridge */ NULL
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};
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static Bool
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ix86PciBusCheck(void)
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{
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PCITAG tag;
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CARD32 id, class;
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CARD8 device;
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for (device = 0; device < ix86Pci0.numDevices; device++) {
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tag = PCI_MAKE_TAG(0, device, 0);
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id = (*ix86Pci0.funcs->pciReadLong)(tag, PCI_ID_REG);
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if ((CARD16)(id + 1U) <= (CARD16)1UL)
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continue;
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/* The rest of this is inspired by the Linux kernel */
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class = (*ix86Pci0.funcs->pciReadLong)(tag, PCI_CLASS_REG);
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/* Ignore revision id and programming interface */
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switch (class >> 16) {
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case (PCI_CLASS_PREHISTORIC << 8) | PCI_SUBCLASS_PREHISTORIC_MISC:
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/* Check for vendors of known buggy chipsets */
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id &= 0x0000ffff;
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if ((id == PCI_VENDOR_INTEL) || (id == PCI_VENDOR_COMPAQ))
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return TRUE;
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continue;
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case (PCI_CLASS_PREHISTORIC << 8) | PCI_SUBCLASS_PREHISTORIC_VGA:
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case (PCI_CLASS_DISPLAY << 8) | PCI_SUBCLASS_DISPLAY_VGA:
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case (PCI_CLASS_BRIDGE << 8) | PCI_SUBCLASS_BRIDGE_HOST:
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return TRUE;
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default:
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break;
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}
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}
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return FALSE;
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}
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static
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void ix86PciSelectCfgmech(void)
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{
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static Bool beenhere = FALSE;
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CARD32 mode1Res1 = 0, mode1Res2 = 0, oldVal1 = 0;
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CARD8 mode2Res1 = 0, mode2Res2 = 0, oldVal2 = 0;
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int stages = 0;
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if (beenhere)
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return; /* Been there, done that */
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beenhere = TRUE;
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/*
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* Determine if motherboard chipset supports PCI Config Mech 1 or 2
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* We rely on xf86Info.pciFlags to tell which mechanisms to try....
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*/
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switch (xf86Info.pciFlags) {
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case PCIOsConfig:
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#ifdef ARCH_PCI_OS_INIT
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return;
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#endif
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case PCIProbe1:
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if (!xf86EnableIO())
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return;
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xf86MsgVerb(X_INFO, 2,
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"PCI: Probing config type using method 1\n");
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oldVal1 = inl(PCI_CFGMECH1_ADDRESS_REG);
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#ifdef DEBUGPCI
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if (xf86Verbose > 2) {
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ErrorF("Checking config type 1:\n"
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"\tinitial value of MODE1_ADDR_REG is 0x%08x\n", oldVal1);
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ErrorF("\tChecking that all bits in mask 0x7f000000 are clear\n");
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}
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#endif
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/* Assuming config type 1 to start with */
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if ((oldVal1 & 0x7f000000) == 0) {
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stages |= 0x01;
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#ifdef DEBUGPCI
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if (xf86Verbose > 2) {
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ErrorF("\tValue indicates possibly config type 1\n");
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ErrorF("\tWriting 32-bit value 0x%08x to MODE1_ADDR_REG\n", PCI_EN);
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#if 0
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ErrorF("\tWriting 8-bit value 0x00 to MODE1_ADDR_REG + 3\n");
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#endif
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}
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#endif
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ix86Pci0.configMech = PCI_CFG_MECH_1;
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ix86Pci0.numDevices = PCI_CFGMECH1_MAXDEV;
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ix86Pci0.funcs = &ix86Funcs1;
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outl(PCI_CFGMECH1_ADDRESS_REG, PCI_EN);
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#if 0
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/*
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* This seems to cause some Neptune-based PCI machines to switch
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* from config type 1 to config type 2
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*/
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outb(PCI_CFGMECH1_ADDRESS_REG + 3, 0);
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#endif
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mode1Res1 = inl(PCI_CFGMECH1_ADDRESS_REG);
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#ifdef DEBUGPCI
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if (xf86Verbose > 2) {
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ErrorF("\tValue read back from MODE1_ADDR_REG is 0x%08x\n",
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mode1Res1);
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ErrorF("\tRestoring original contents of MODE1_ADDR_REG\n");
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}
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#endif
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outl(PCI_CFGMECH1_ADDRESS_REG, oldVal1);
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if (mode1Res1) {
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stages |= 0x02;
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#ifdef DEBUGPCI
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if (xf86Verbose > 2) {
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ErrorF("\tValue read back is non-zero, and indicates possible"
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" config type 1\n");
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}
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#endif
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if (ix86PciBusCheck()) {
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#ifdef DEBUGPCI
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if (xf86Verbose > 2)
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ErrorF("\tBus check Confirms this: ");
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#endif
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xf86MsgVerb(X_INFO, 2, "PCI: Config type is 1\n");
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xf86MsgVerb(X_INFO, 3,
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"PCI: stages = 0x%02x, oldVal1 = 0x%08lx, mode1Res1"
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" = 0x%08lx\n", stages, (unsigned long)oldVal1,
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(unsigned long)mode1Res1);
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return;
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}
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#ifdef DEBUGPCI
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if (xf86Verbose > 2) {
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ErrorF("\tBus check fails to confirm this, continuing type 1"
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" check ...\n");
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}
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#endif
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}
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stages |= 0x04;
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#ifdef DEBUGPCI
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if (xf86Verbose > 2) {
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ErrorF("\tWriting 0xff000001 to MODE1_ADDR_REG\n");
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}
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#endif
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outl(PCI_CFGMECH1_ADDRESS_REG, 0xff000001);
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mode1Res2 = inl(PCI_CFGMECH1_ADDRESS_REG);
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#ifdef DEBUGPCI
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if (xf86Verbose > 2) {
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ErrorF("\tValue read back from MODE1_ADDR_REG is 0x%08x\n",
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mode1Res2);
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ErrorF("\tRestoring original contents of MODE1_ADDR_REG\n");
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}
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#endif
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outl(PCI_CFGMECH1_ADDRESS_REG, oldVal1);
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if ((mode1Res2 & 0x80000001) == 0x80000000) {
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stages |= 0x08;
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#ifdef DEBUGPCI
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if (xf86Verbose > 2) {
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ErrorF("\tValue read back has only the msb set\n"
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"\tThis indicates possible config type 1\n");
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}
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#endif
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if (ix86PciBusCheck()) {
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#ifdef DEBUGPCI
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if (xf86Verbose > 2)
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ErrorF("\tBus check Confirms this: ");
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#endif
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xf86MsgVerb(X_INFO, 2, "PCI: Config type is 1\n");
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xf86MsgVerb(X_INFO, 3,
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"PCI: stages = 0x%02x, oldVal1 = 0x%08lx,\n"
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"\tmode1Res1 = 0x%08lx, mode1Res2 = 0x%08lx\n",
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stages, (unsigned long)oldVal1,
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(unsigned long)mode1Res1, (unsigned long)mode1Res2);
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return;
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}
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#ifdef DEBUGPCI
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if (xf86Verbose > 2) {
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ErrorF("\tBus check fails to confirm this.\n");
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}
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#endif
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}
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}
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xf86MsgVerb(X_INFO, 3, "PCI: Standard check for type 1 failed.\n");
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xf86MsgVerb(X_INFO, 3, "PCI: stages = 0x%02x, oldVal1 = 0x%08lx,\n"
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"\tmode1Res1 = 0x%08lx, mode1Res2 = 0x%08lx\n",
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stages, (unsigned long)oldVal1, (unsigned long)mode1Res1,
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(unsigned long)mode1Res2);
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/* Try config type 2 */
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oldVal2 = inb(PCI_CFGMECH2_ENABLE_REG);
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if ((oldVal2 & 0xf0) == 0) {
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ix86Pci0.configMech = PCI_CFG_MECH_2;
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ix86Pci0.numDevices = PCI_CFGMECH2_MAXDEV;
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ix86Pci0.funcs = &ix86Funcs2;
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outb(PCI_CFGMECH2_ENABLE_REG, 0x0e);
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mode2Res1 = inb(PCI_CFGMECH2_ENABLE_REG);
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outb(PCI_CFGMECH2_ENABLE_REG, oldVal2);
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if (mode2Res1 == 0x0e) {
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if (ix86PciBusCheck()) {
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xf86MsgVerb(X_INFO, 2, "PCI: Config type is 2\n");
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return;
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}
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}
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}
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break; /* } */
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case PCIProbe2: /* { */
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if (!xf86EnableIO())
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return;
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/* The scanpci-style detection method */
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xf86MsgVerb(X_INFO, 2, "PCI: Probing config type using method 2\n");
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outb(PCI_CFGMECH2_ENABLE_REG, 0x00);
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outb(PCI_CFGMECH2_FORWARD_REG, 0x00);
|
|
mode2Res1 = inb(PCI_CFGMECH2_ENABLE_REG);
|
|
mode2Res2 = inb(PCI_CFGMECH2_FORWARD_REG);
|
|
|
|
if (mode2Res1 == 0 && mode2Res2 == 0) {
|
|
xf86MsgVerb(X_INFO, 2, "PCI: Config type is 2\n");
|
|
ix86Pci0.configMech = PCI_CFG_MECH_2;
|
|
ix86Pci0.numDevices = PCI_CFGMECH2_MAXDEV;
|
|
ix86Pci0.funcs = &ix86Funcs2;
|
|
return;
|
|
}
|
|
|
|
oldVal1 = inl(PCI_CFGMECH1_ADDRESS_REG);
|
|
outl(PCI_CFGMECH1_ADDRESS_REG, PCI_EN);
|
|
mode1Res1 = inl(PCI_CFGMECH1_ADDRESS_REG);
|
|
outl(PCI_CFGMECH1_ADDRESS_REG, oldVal1);
|
|
if (mode1Res1 == PCI_EN) {
|
|
xf86MsgVerb(X_INFO, 2, "PCI: Config type is 1\n");
|
|
ix86Pci0.configMech = PCI_CFG_MECH_1;
|
|
ix86Pci0.numDevices = PCI_CFGMECH1_MAXDEV;
|
|
ix86Pci0.funcs = &ix86Funcs1;
|
|
return;
|
|
}
|
|
break; /* } */
|
|
|
|
case PCIForceConfig1:
|
|
if (!xf86EnableIO())
|
|
return;
|
|
|
|
xf86MsgVerb(X_INFO, 2, "PCI: Forcing config type 1\n");
|
|
|
|
ix86Pci0.configMech = PCI_CFG_MECH_1;
|
|
ix86Pci0.numDevices = PCI_CFGMECH1_MAXDEV;
|
|
ix86Pci0.funcs = &ix86Funcs1;
|
|
return;
|
|
|
|
case PCIForceConfig2:
|
|
if (!xf86EnableIO())
|
|
return;
|
|
|
|
xf86MsgVerb(X_INFO, 2, "PCI: Forcing config type 2\n");
|
|
|
|
ix86Pci0.configMech = PCI_CFG_MECH_2;
|
|
ix86Pci0.numDevices = PCI_CFGMECH2_MAXDEV;
|
|
ix86Pci0.funcs = &ix86Funcs2;
|
|
return;
|
|
|
|
case PCIForceNone:
|
|
break;
|
|
}
|
|
|
|
/* No PCI found */
|
|
ix86Pci0.configMech = PCI_CFG_MECH_UNKNOWN;
|
|
xf86MsgVerb(X_INFO, 2, "PCI: No PCI bus found or probed for\n");
|
|
}
|
|
|
|
#if 0
|
|
static pciTagRec
|
|
ix86PcibusTag(CARD8 bus, CARD8 cardnum, CARD8 func)
|
|
{
|
|
pciTagRec tag;
|
|
|
|
tag.cfg1 = 0;
|
|
|
|
if (func > 7 || cardnum >= pciBusInfo[bus]->numDevices)
|
|
return tag;
|
|
|
|
switch (ix86Pci0.configMech) {
|
|
case PCI_CFG_MECH_1:
|
|
tag.cfg1 = PCI_EN | ((CARD32)bus << 16) |
|
|
((CARD32)cardnum << 11) |
|
|
((CARD32)func << 8);
|
|
break;
|
|
|
|
case PCI_CFG_MECH_2:
|
|
tag.cfg2.port = 0xc000 | ((CARD16)cardnum << 8);
|
|
tag.cfg2.enable = 0xf0 | (func << 1);
|
|
tag.cfg2.forward = bus;
|
|
break;
|
|
}
|
|
|
|
return tag;
|
|
}
|
|
#endif
|
|
|
|
static CARD32
|
|
ix86PciReadLongSetup(PCITAG Tag, int reg)
|
|
{
|
|
ix86PciSelectCfgmech();
|
|
return (*ix86Pci0.funcs->pciReadLong)(Tag,reg);
|
|
}
|
|
|
|
static CARD32
|
|
ix86PciReadLongCFG1(PCITAG Tag, int reg)
|
|
{
|
|
CARD32 addr, data = 0;
|
|
|
|
#ifdef DEBUGPCI
|
|
ErrorF("ix86PciReadLong 0x%lx, %d\n", Tag, reg);
|
|
#endif
|
|
|
|
addr = PCI_ADDR_FROM_TAG_CFG1(Tag,reg);
|
|
outl(PCI_CFGMECH1_ADDRESS_REG, addr);
|
|
data = inl(PCI_CFGMECH1_DATA_REG);
|
|
outl(PCI_CFGMECH1_ADDRESS_REG, 0);
|
|
|
|
#ifdef DEBUGPCI
|
|
ErrorF("ix86PciReadLong 0x%lx\n", data);
|
|
#endif
|
|
|
|
return data;
|
|
}
|
|
|
|
static CARD32
|
|
ix86PciReadLongCFG2(PCITAG Tag, int reg)
|
|
{
|
|
CARD32 addr, data = 0;
|
|
CARD8 forward, enable;
|
|
|
|
#ifdef DEBUGPCI
|
|
ErrorF("ix86PciReadLong 0x%lx, %d\n", Tag, reg);
|
|
#endif
|
|
|
|
forward = PCI_FORWARD_FROM_TAG(Tag);
|
|
enable = PCI_ENABLE_FROM_TAG(Tag);
|
|
addr = PCI_ADDR_FROM_TAG_CFG2(Tag,reg);
|
|
|
|
outb(PCI_CFGMECH2_ENABLE_REG, enable);
|
|
outb(PCI_CFGMECH2_FORWARD_REG, forward);
|
|
data = inl((CARD16)addr);
|
|
outb(PCI_CFGMECH2_ENABLE_REG, 0);
|
|
outb(PCI_CFGMECH2_FORWARD_REG, 0);
|
|
|
|
#ifdef DEBUGPCI
|
|
ErrorF("ix86PciReadLong 0x%lx\n", data);
|
|
#endif
|
|
|
|
return data;
|
|
}
|
|
|
|
static void
|
|
ix86PciWriteLongSetup(PCITAG Tag, int reg, CARD32 data)
|
|
{
|
|
ix86PciSelectCfgmech();
|
|
(*ix86Pci0.funcs->pciWriteLong)(Tag,reg,data);
|
|
}
|
|
|
|
static void
|
|
ix86PciWriteLongCFG1(PCITAG Tag, int reg, CARD32 data)
|
|
{
|
|
CARD32 addr;
|
|
|
|
addr = PCI_ADDR_FROM_TAG_CFG1(Tag,reg);
|
|
outl(PCI_CFGMECH1_ADDRESS_REG, addr);
|
|
outl(PCI_CFGMECH1_DATA_REG, data);
|
|
outl(PCI_CFGMECH1_ADDRESS_REG, 0);
|
|
}
|
|
|
|
static void
|
|
ix86PciWriteLongCFG2(PCITAG Tag, int reg, CARD32 data)
|
|
{
|
|
CARD32 addr;
|
|
CARD8 forward, enable;
|
|
|
|
forward = PCI_FORWARD_FROM_TAG(Tag);
|
|
enable = PCI_ENABLE_FROM_TAG(Tag);
|
|
addr = PCI_ADDR_FROM_TAG_CFG2(Tag,reg);
|
|
|
|
outb(PCI_CFGMECH2_ENABLE_REG, enable);
|
|
outb(PCI_CFGMECH2_FORWARD_REG, forward);
|
|
outl((CARD16)addr, data);
|
|
outb(PCI_CFGMECH2_ENABLE_REG, 0);
|
|
outb(PCI_CFGMECH2_FORWARD_REG, 0);
|
|
}
|
|
|
|
static void
|
|
ix86PciSetBitsLongSetup(PCITAG Tag, int reg, CARD32 mask, CARD32 val)
|
|
{
|
|
ix86PciSelectCfgmech();
|
|
(*ix86Pci0.funcs->pciSetBitsLong)(Tag,reg,mask,val);
|
|
}
|
|
|
|
static void
|
|
ix86PciSetBitsLongCFG1(PCITAG Tag, int reg, CARD32 mask, CARD32 val)
|
|
{
|
|
CARD32 addr, data = 0;
|
|
|
|
#ifdef DEBUGPCI
|
|
ErrorF("ix86PciSetBitsLong 0x%lx, %d\n", Tag, reg);
|
|
#endif
|
|
|
|
addr = PCI_ADDR_FROM_TAG_CFG1(Tag,reg);
|
|
outl(PCI_CFGMECH1_ADDRESS_REG, addr);
|
|
data = inl(PCI_CFGMECH1_DATA_REG);
|
|
data = (data & ~mask) | (val & mask);
|
|
outl(PCI_CFGMECH1_DATA_REG, data);
|
|
outl(PCI_CFGMECH1_ADDRESS_REG, 0);
|
|
}
|
|
|
|
static void
|
|
ix86PciSetBitsLongCFG2(PCITAG Tag, int reg, CARD32 mask, CARD32 val)
|
|
{
|
|
CARD32 addr, data = 0;
|
|
CARD8 enable, forward;
|
|
|
|
#ifdef DEBUGPCI
|
|
ErrorF("ix86PciSetBitsLong 0x%lx, %d\n", Tag, reg);
|
|
#endif
|
|
|
|
forward = PCI_FORWARD_FROM_TAG(Tag);
|
|
enable = PCI_ENABLE_FROM_TAG(Tag);
|
|
addr = PCI_ADDR_FROM_TAG_CFG2(Tag,reg);
|
|
|
|
outb(PCI_CFGMECH2_ENABLE_REG, enable);
|
|
outb(PCI_CFGMECH2_FORWARD_REG, forward);
|
|
data = inl((CARD16)addr);
|
|
data = (data & ~mask) | (val & mask);
|
|
outl((CARD16)addr, data);
|
|
outb(PCI_CFGMECH2_ENABLE_REG, 0);
|
|
outb(PCI_CFGMECH2_FORWARD_REG, 0);
|
|
}
|
|
|
|
void
|
|
ix86PciInit()
|
|
{
|
|
/* Initialize pciBusInfo[] array and function pointers */
|
|
pciNumBuses = 1;
|
|
pciBusInfo[0] = &ix86Pci0;
|
|
pciFindFirstFP = pciGenFindFirst;
|
|
pciFindNextFP = pciGenFindNext;
|
|
|
|
/* Make sure that there is a PCI bus present. */
|
|
ix86PciSelectCfgmech();
|
|
if (ix86Pci0.configMech == PCI_CFG_MECH_UNKNOWN) {
|
|
pciNumBuses = 0;
|
|
pciBusInfo[0] = NULL;
|
|
}
|
|
}
|