d23c46dd3e
permissions when no access to HW registers is required. For API changes
which mostly involve the modifications to make the RRFunc (introduced
with 6.8) more flexible please check Bugzilla #2407. NOTE: This patch
applies changes to OS specific files for other OSes which I cannot
test.
308 lines
8.4 KiB
C
308 lines
8.4 KiB
C
/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/ppcPci.c,v 1.8 2002/07/24 19:06:52 tsi Exp $ */
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/*
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* ppcPci.c - PowerPC PCI access functions
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*
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* PCI driver functions supporting Motorola PowerPC platforms
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* including Powerstack(RiscPC/RiscPC+), PowerStackII, MTX, and
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* MVME 160x/260x/360x/460x VME boards
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*
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* Gary Barton
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* Concurrent Computer Corporation
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* garyb@gate.net
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*
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*/
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/*
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* Copyright 1998 by Concurrent Computer Corporation
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*
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* Permission to use, copy, modify, distribute, and sell this software
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* and its documentation for any purpose is hereby granted without fee,
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* provided that the above copyright notice appear in all copies and that
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* both that copyright notice and this permission notice appear in
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* supporting documentation, and that the name of Concurrent Computer
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* Corporation not be used in advertising or publicity pertaining to
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* distribution of the software without specific, written prior
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* permission. Concurrent Computer Corporation makes no representations
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* about the suitability of this software for any purpose. It is
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* provided "as is" without express or implied warranty.
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*
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* CONCURRENT COMPUTER CORPORATION DISCLAIMS ALL WARRANTIES WITH REGARD
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* TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS, IN NO EVENT SHALL CONCURRENT COMPUTER CORPORATION BE
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* LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
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* DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
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* WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
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* ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
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* SOFTWARE.
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*
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* Copyright 1998 by Metro Link Incorporated
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*
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* Permission to use, copy, modify, distribute, and sell this software
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* and its documentation for any purpose is hereby granted without fee,
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* provided that the above copyright notice appear in all copies and that
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* both that copyright notice and this permission notice appear in
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* supporting documentation, and that the name of Metro Link
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* Incorporated not be used in advertising or publicity pertaining to
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* distribution of the software without specific, written prior
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* permission. Metro Link Incorporated makes no representations
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* about the suitability of this software for any purpose. It is
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* provided "as is" without express or implied warranty.
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*
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* METRO LINK INCORPORATED DISCLAIMS ALL WARRANTIES WITH REGARD
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* TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS, IN NO EVENT SHALL METRO LINK INCORPORATED BE
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* LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
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* DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
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* WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
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* ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
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* SOFTWARE.
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*/
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#include <stdio.h>
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#include "compiler.h"
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#include "xf86.h"
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#include "xf86Priv.h"
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#include "xf86_OSlib.h"
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#include "Pci.h"
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#ifndef MAP_FAILED
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#define MAP_FAILED (pointer)(-1)
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#endif
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void
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ppcPciInit()
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{
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#if defined(PowerMAX_OS)
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extern void pmaxPciInit(void);
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pmaxPciInit();
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#else
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static void motoppcPciInit(void);
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motoppcPciInit();
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#endif
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}
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#if defined(PowerMAX_OS)
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/*
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* Motorola PowerPC platform support
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*
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* The following code should support the MVME 1600 & 2600 VME boards
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* as well as the various PowerStack and RiscPC models. All of these
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* machines support PCI config mechanism #1 and use the std config
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* address and data regs locations:
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* cfg address reg = 0xcf8 (PCI I/O)
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* cfg data reg = 0xcfc (PCI I/O)
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*
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* The moto machines do have different address maps on either side
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* of the PCI-host bridge though.
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*/
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static ADDRESS motoppcBusAddrToHostAddr(PCITAG, PciAddrType, ADDRESS);
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static ADDRESS motoppcHostAddrToBusAddr(PCITAG, PciAddrType, ADDRESS);
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static CARD32 pciCfgMech1Read(PCITAG tag, int offset);
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static void pciCfgMech1Write(PCITAG tag, int offset, CARD32 val);
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static void pciCfgMech1SetBits(PCITAG tag, int offset,
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CARD32 mask, CARD32 val);
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static pciBusFuncs_t motoppcFuncs0 = {
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/* pciReadLong */ pciCfgMech1Read,
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/* pciWriteLong */ pciCfgMech1Write,
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/* pciSetBitsLong */ pciCfgMech1SetBits,
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/* pciAddrHostToBus */ motoppcHostAddrToBusAddr,
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/* pciAddrBusToHost */ motoppcBusAddrToHostAddr
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};
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static pciBusInfo_t motoppcPci0 = {
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/* configMech */ PCI_CFG_MECH_1,
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/* numDevices */ 32,
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/* secondary */ FALSE,
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/* primary_bus */ 0,
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#ifdef PowerMAX_OS
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/* ppc_io_base */ 0x80000000,
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/* ppc_io_size */ 64 * 1024,
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#endif
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/* funcs */ &motoppcFuncs0,
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/* pciBusPriv */ NULL,
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/* bridge */ NULL
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};
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extern volatile unsigned char *ioBase;
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static void
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motoppcPciInit()
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{
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pciNumBuses = 1;
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pciBusInfo[0] = &motoppcPci0;
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pciFindFirstFP = pciGenFindFirst;
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pciFindNextFP = pciGenFindNext;
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if (!xf86EnableIO())
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FatalError("motoppcPciInit: EnableIO failed\n");
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if (ioBase == MAP_FAILED) {
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ppcPciIoMap(0); /* Make inb/outb et al work for pci0 and its secondaries */
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if (ioBase == MAP_FAILED) {
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FatalError("motoppcPciInit: Cannot map pci0 I/O segment!!!\n");
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/*NOTREACHED*/
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}
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}
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}
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extern unsigned long motoPciMemBase = 0;
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#if defined(Lynx) && defined(__powerpc__)
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extern unsigned long motoPciMemLen = 0x40000000;
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#else
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extern unsigned long motoPciMemLen = 0x3f000000;
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#endif
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extern unsigned long motoPciMemBaseCPU = 0xc0000000;
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static ADDRESS
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motoppcBusAddrToHostAddr(PCITAG tag, PciAddrType type, ADDRESS addr)
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{
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unsigned long addr_l = (unsigned long)addr;
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if (type == PCI_MEM) {
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if (addr_l >= motoPciMemBase && addr_l < motoPciMemLen)
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/*
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* PCI memory space addresses [0-0x3effffff] are
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* are seen at [0xc0000000,0xfeffffff] on moto host
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*/
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return((ADDRESS)((motoPciMemBaseCPU - motoPciMemBase) + addr_l));
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else if (addr_l >= 0x80000000)
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/*
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* Moto host memory [0,0x7fffffff] is seen at
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* [0x80000000,0xffffffff] on PCI bus
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*/
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return((ADDRESS)(addr_l & 0x7fffffff));
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else
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FatalError("motoppcBusAddrToHostAddr: PCI addr 0x%x is not accessible to host!!!\n",
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addr_l);
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} else
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return addr;
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/*NOTREACHED*/
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}
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static ADDRESS
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motoppcHostAddrToBusAddr(PCITAG tag, PciAddrType type, ADDRESS addr)
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{
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unsigned long addr_l = (unsigned long)addr;
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if (type == PCI_MEM) {
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if (addr_l < 0x80000000)
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/*
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* Moto host memory [0,0x7fffffff] is seen at
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* [0x80000000,0xffffffff] on PCI bus
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*/
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return((ADDRESS)(0x80000000 | addr_l));
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else if (addr_l >= motoPciMemBaseCPU && addr_l < motoPciMemBaseCPU + motoPciMemLen)
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/*
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* PCI memory space addresses [0-0x3effffff] are
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* are seen at [0xc0000000,0xfeffffff] on moto host
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*/
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return((ADDRESS)(addr_l - (motoPciMemBaseCPU - motoPciMemBase)));
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else
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FatalError("motoppcHostAddrToBusAddr: Host addr 0x%x is not accessible to PCI!!!\n",
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addr_l);
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} else
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return addr;
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/*NOTREACHED*/
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}
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#if defined (__powerpc__)
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static int buserr_detected;
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static
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void buserr(int sig)
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{
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buserr_detected = 1;
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}
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#endif
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static CARD32
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pciCfgMech1Read(PCITAG tag, int offset)
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{
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unsigned long rv = 0xffffffff;
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#ifdef DEBUGPCI
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ErrorF("pciCfgMech1Read(tag=%08x,offset=%08x)\n", tag, offset);
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#endif
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#if defined(__powerpc__)
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signal(SIGBUS, buserr);
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buserr_detected = 0;
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#endif
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outl(0xCF8, PCI_EN | tag | (offset & 0xfc));
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rv = inl(0xCFC);
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#if defined(__powerpc__)
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signal(SIGBUS, SIG_DFL);
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if (buserr_detected)
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{
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#ifdef DEBUGPCI
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ErrorF("pciCfgMech1Read() BUS ERROR\n");
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#endif
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return(0xffffffff);
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}
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else
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#endif
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return(rv);
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}
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static void
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pciCfgMech1Write(PCITAG tag, int offset, CARD32 val)
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{
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#ifdef DEBUGPCI
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ErrorF("pciCfgMech1Write(tag=%08x,offset=%08x,val=%08x)\n",
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tag, offset,val);
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#endif
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#if defined(__powerpc__)
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signal(SIGBUS, SIG_IGN);
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#endif
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outl(0xCF8, PCI_EN | tag | (offset & 0xfc));
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#if defined(Lynx) && defined(__powerpc__)
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outb(0x80, 0x00); /* without this the next access fails
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* on my Powerstack system when we use
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* assembler inlines for outl */
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#endif
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outl(0xCFC, val);
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#if defined(__powerpc__)
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signal(SIGBUS, SIG_DFL);
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#endif
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}
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static void
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pciCfgMech1SetBits(PCITAG tag, int offset, CARD32 mask, CARD32 val)
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{
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unsigned long rv = 0xffffffff;
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#if defined(__powerpc__)
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signal(SIGBUS, buserr);
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#endif
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outl(0xCF8, PCI_EN | tag | (offset & 0xfc));
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rv = inl(0xCFC);
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rv = (rv & ~mask) | val;
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outl(0xCFC, rv);
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#if defined(__powerpc__)
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signal(SIGBUS, SIG_DFL);
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#endif
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}
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#endif /* PowerMAX_OS */
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