951 lines
25 KiB
C
951 lines
25 KiB
C
/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/linuxPci.c,v 1.9 2002/09/24 16:14:16 tsi Exp $ */
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/*
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* Copyright 1998 by Concurrent Computer Corporation
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*
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* Permission to use, copy, modify, distribute, and sell this software
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* and its documentation for any purpose is hereby granted without fee,
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* provided that the above copyright notice appear in all copies and that
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* both that copyright notice and this permission notice appear in
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* supporting documentation, and that the name of Concurrent Computer
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* Corporation not be used in advertising or publicity pertaining to
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* distribution of the software without specific, written prior
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* permission. Concurrent Computer Corporation makes no representations
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* about the suitability of this software for any purpose. It is
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* provided "as is" without express or implied warranty.
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*
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* CONCURRENT COMPUTER CORPORATION DISCLAIMS ALL WARRANTIES WITH REGARD
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* TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS, IN NO EVENT SHALL CONCURRENT COMPUTER CORPORATION BE
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* LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
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* DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
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* WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
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* ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
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* SOFTWARE.
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*
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* Copyright 1998 by Metro Link Incorporated
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*
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* Permission to use, copy, modify, distribute, and sell this software
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* and its documentation for any purpose is hereby granted without fee,
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* provided that the above copyright notice appear in all copies and that
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* both that copyright notice and this permission notice appear in
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* supporting documentation, and that the name of Metro Link
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* Incorporated not be used in advertising or publicity pertaining to
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* distribution of the software without specific, written prior
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* permission. Metro Link Incorporated makes no representations
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* about the suitability of this software for any purpose. It is
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* provided "as is" without express or implied warranty.
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*
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* METRO LINK INCORPORATED DISCLAIMS ALL WARRANTIES WITH REGARD
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* TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS, IN NO EVENT SHALL METRO LINK INCORPORATED BE
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* LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
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* DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
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* WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
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* ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
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* SOFTWARE.
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*/
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#ifdef HAVE_XORG_CONFIG_H
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#include <xorg-config.h>
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#endif
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#include <stdio.h>
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#include "compiler.h"
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#include "xf86.h"
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#include "xf86Priv.h"
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#include "xf86_OSlib.h"
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#include "Pci.h"
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/*
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* linux platform specific PCI access functions -- using /proc/bus/pci
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* needs kernel version 2.2.x
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*/
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static CARD32 linuxPciCfgRead(PCITAG tag, int off);
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static void linuxPciCfgWrite(PCITAG, int off, CARD32 val);
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static void linuxPciCfgSetBits(PCITAG tag, int off, CARD32 mask, CARD32 bits);
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static ADDRESS linuxTransAddrBusToHost(PCITAG tag, PciAddrType type, ADDRESS addr);
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#if defined(__powerpc__)
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static ADDRESS linuxPpcBusAddrToHostAddr(PCITAG, PciAddrType, ADDRESS);
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static ADDRESS linuxPpcHostAddrToBusAddr(PCITAG, PciAddrType, ADDRESS);
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#endif
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static CARD8 linuxPciCfgReadByte(PCITAG tag, int off);
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static void linuxPciCfgWriteByte(PCITAG tag, int off, CARD8 val);
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static CARD16 linuxPciCfgReadWord(PCITAG tag, int off);
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static void linuxPciCfgWriteWord(PCITAG tag, int off, CARD16 val);
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static int linuxPciHandleBIOS(PCITAG Tag, int basereg, unsigned char *buf, int len);
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static pciBusFuncs_t linuxFuncs0 = {
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/* pciReadLong */ linuxPciCfgRead,
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/* pciWriteLong */ linuxPciCfgWrite,
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/* pciSetBitsLong */ linuxPciCfgSetBits,
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#if defined(__powerpc__)
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/* pciAddrHostToBus */ linuxPpcHostAddrToBusAddr,
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/* pciAddrBusToHost */ linuxPpcBusAddrToHostAddr,
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#else
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/* pciAddrHostToBus */ pciAddrNOOP,
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/* pciAddrBusToHost */ linuxTransAddrBusToHost,
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#endif
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/* pciControlBridge */ NULL,
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/* pciGetBridgeBuses */ NULL,
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/* pciGetBridgeResources */ NULL,
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/* pciReadByte */ linuxPciCfgReadByte,
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/* pciWriteByte */ linuxPciCfgWriteByte,
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/* pciReadWord */ linuxPciCfgReadWord,
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/* pciWriteWord */ linuxPciCfgWriteWord,
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};
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static pciBusInfo_t linuxPci0 = {
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/* configMech */ PCI_CFG_MECH_OTHER,
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/* numDevices */ 32,
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/* secondary */ FALSE,
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/* primary_bus */ 0,
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/* funcs */ &linuxFuncs0,
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/* pciBusPriv */ NULL,
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/* bridge */ NULL
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};
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/* from lnx_pci.c. */
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extern int lnxPciInit(void);
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void
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linuxPciInit()
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{
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struct stat st;
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if ((xf86Info.pciFlags == PCIForceNone) ||
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(-1 == stat("/proc/bus/pci", &st))) {
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/* when using this as default for all linux architectures,
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we'll need a fallback for 2.0 kernels here */
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return;
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}
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pciNumBuses = 1;
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pciBusInfo[0] = &linuxPci0;
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pciFindFirstFP = pciGenFindFirst;
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pciFindNextFP = pciGenFindNext;
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pciSetOSBIOSPtr(linuxPciHandleBIOS);
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xf86MaxPciDevs = lnxPciInit();
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}
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static int
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linuxPciOpenFile(PCITAG tag, Bool write)
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{
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static int lbus,ldev,lfunc,fd = -1,is_write = 0;
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int bus, dev, func;
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char file[64];
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struct stat ignored;
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static int is26 = -1;
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bus = PCI_BUS_FROM_TAG(tag);
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dev = PCI_DEV_FROM_TAG(tag);
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func = PCI_FUNC_FROM_TAG(tag);
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if (is26 == -1) {
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if (stat("/sys/bus/pci",&ignored) < 0)
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is26 = 0;
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else
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is26 = 1;
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}
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if (fd == -1 || (write && (!is_write))
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|| bus != lbus || dev != ldev || func != lfunc) {
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if (fd != -1)
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close(fd);
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if (is26)
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sprintf(file,"/sys/bus/pci/devices/0000:%02x:%02x.%01x/config",
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bus, dev, func);
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else {
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if (bus < 256) {
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sprintf(file,"/proc/bus/pci/%02x",bus);
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if (stat(file, &ignored) < 0)
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sprintf(file, "/proc/bus/pci/0000:%02x/%02x.%1x",
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bus, dev, func);
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else
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sprintf(file, "/proc/bus/pci/%02x/%02x.%1x",
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bus, dev, func);
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} else {
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sprintf(file,"/proc/bus/pci/%04x",bus);
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if (stat(file, &ignored) < 0)
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sprintf(file, "/proc/bus/pci/0000:%04x/%02x.%1x",
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bus, dev, func);
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else
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sprintf(file, "/proc/bus/pci/%04x/%02x.%1x",
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bus, dev, func);
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}
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}
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if (write) {
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fd = open(file,O_RDWR);
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if (fd != -1) is_write = TRUE;
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} else switch (is_write) {
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case TRUE:
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fd = open(file,O_RDWR);
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if (fd > -1)
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break;
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default:
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fd = open(file,O_RDONLY);
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is_write = FALSE;
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}
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lbus = bus;
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ldev = dev;
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lfunc = func;
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}
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return fd;
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}
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static CARD32
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linuxPciCfgRead(PCITAG tag, int off)
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{
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int fd;
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CARD32 val = 0xffffffff;
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if (-1 != (fd = linuxPciOpenFile(tag,FALSE))) {
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lseek(fd,off,SEEK_SET);
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read(fd,&val,4);
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}
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return PCI_CPU(val);
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}
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static void
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linuxPciCfgWrite(PCITAG tag, int off, CARD32 val)
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{
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int fd;
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if (-1 != (fd = linuxPciOpenFile(tag,TRUE))) {
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lseek(fd,off,SEEK_SET);
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val = PCI_CPU(val);
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write(fd,&val,4);
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}
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}
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static void
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linuxPciCfgSetBits(PCITAG tag, int off, CARD32 mask, CARD32 bits)
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{
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int fd;
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CARD32 val = 0xffffffff;
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if (-1 != (fd = linuxPciOpenFile(tag,TRUE))) {
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lseek(fd,off,SEEK_SET);
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read(fd,&val,4);
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val = PCI_CPU(val);
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val = (val & ~mask) | (bits & mask);
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val = PCI_CPU(val);
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lseek(fd,off,SEEK_SET);
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write(fd,&val,4);
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}
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}
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/*
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* This function will convert a BAR address into a host address
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* suitable for passing into the mmap function of a /proc/bus
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* device.
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*/
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ADDRESS linuxTransAddrBusToHost(PCITAG tag, PciAddrType type, ADDRESS addr)
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{
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ADDRESS ret = xf86GetOSOffsetFromPCI(tag, PCI_MEM|PCI_IO, addr);
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if (ret)
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return ret;
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/*
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* if it is not a BAR address, it must be legacy, (or wrong)
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* return it as is..
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*/
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return addr;
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}
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#if defined(__powerpc__)
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#ifndef __NR_pciconfig_iobase
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#define __NR_pciconfig_iobase 200
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#endif
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static ADDRESS
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linuxPpcBusAddrToHostAddr(PCITAG tag, PciAddrType type, ADDRESS addr)
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{
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if (type == PCI_MEM)
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{
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ADDRESS membase = syscall(__NR_pciconfig_iobase, 1,
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PCI_BUS_FROM_TAG(tag), PCI_DFN_FROM_TAG(tag));
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return (addr + membase);
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}
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else if (type == PCI_IO)
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{
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ADDRESS iobase = syscall(__NR_pciconfig_iobase, 2,
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PCI_BUS_FROM_TAG(tag), PCI_DFN_FROM_TAG(tag));
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return (addr + iobase);
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}
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else return addr;
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}
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static ADDRESS
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linuxPpcHostAddrToBusAddr(PCITAG tag, PciAddrType type, ADDRESS addr)
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{
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if (type == PCI_MEM)
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{
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ADDRESS membase = syscall(__NR_pciconfig_iobase, 1,
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PCI_BUS_FROM_TAG(tag), PCI_DFN_FROM_TAG(tag));
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return (addr - membase);
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}
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else if (type == PCI_IO)
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{
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ADDRESS iobase = syscall(__NR_pciconfig_iobase, 2,
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PCI_BUS_FROM_TAG(tag), PCI_DFN_FROM_TAG(tag));
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return (addr - iobase);
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}
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else return addr;
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}
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#endif /* __powerpc__ */
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static CARD8
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linuxPciCfgReadByte(PCITAG tag, int off)
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{
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int fd;
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CARD8 val = 0xff;
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if (-1 != (fd = linuxPciOpenFile(tag,FALSE))) {
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lseek(fd,off,SEEK_SET);
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read(fd,&val,1);
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}
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return val;
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}
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static void
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linuxPciCfgWriteByte(PCITAG tag, int off, CARD8 val)
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{
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int fd;
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if (-1 != (fd = linuxPciOpenFile(tag,TRUE))) {
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lseek(fd,off,SEEK_SET);
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write(fd, &val, 1);
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}
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}
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static CARD16
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linuxPciCfgReadWord(PCITAG tag, int off)
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{
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int fd;
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CARD16 val = 0xff;
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if (-1 != (fd = linuxPciOpenFile(tag,FALSE))) {
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lseek(fd, off, SEEK_SET);
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read(fd, &val, 2);
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}
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return PCI_CPU16(val);
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}
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static void
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linuxPciCfgWriteWord(PCITAG tag, int off, CARD16 val)
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{
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int fd;
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if (-1 != (fd = linuxPciOpenFile(tag,TRUE))) {
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lseek(fd, off, SEEK_SET);
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val = PCI_CPU16(val);
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write(fd, &val, 2);
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}
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}
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#ifndef INCLUDE_XF86_NO_DOMAIN
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/*
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* Compiling the following simply requires the presence of <linux/pci.c>.
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* Actually running this is another matter altogether...
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*
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* This scheme requires that the kernel allow mmap()'ing of a host bridge's I/O
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* and memory spaces through its /proc/bus/pci/BUS/DFN entry. Which one is
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* determined by a prior ioctl().
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*
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* For the sparc64 port, this means 2.4.12 or later. For ppc, this
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* functionality is almost, but not quite there yet. Alpha and other kernel
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* ports to multi-domain architectures still need to implement this.
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*
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* This scheme is also predicated on the use of an IOADDRESS compatible type to
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* designate I/O addresses. Although IOADDRESS is defined as an unsigned
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* integral type, it is actually the virtual address of, i.e. a pointer to, the
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* I/O port to access. And so, the inX/outX macros in "compiler.h" need to be
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* #define'd appropriately (as is done on SPARC's).
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*
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* Another requirement to port this scheme to another multi-domain architecture
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* is to add the appropriate entries in the pciControllerSizes array below.
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*
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* TO DO: Address the deleterious reaction some host bridges have to master
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* aborts. This is already done for secondary PCI buses, but not yet
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* for accesses to primary buses (except for the SPARC port, where
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* master aborts are avoided during PCI scans).
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*/
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#include <linux/pci.h>
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#ifndef PCIIOC_BASE /* Ioctls for /proc/bus/pci/X/Y nodes. */
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#define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
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/* Get controller for PCI device. */
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#define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00)
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/* Set mmap state to I/O space. */
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#define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01)
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/* Set mmap state to MEM space. */
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#define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02)
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/* Enable/disable write-combining. */
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#define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03)
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#endif
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/* This probably shouldn't be Linux-specific */
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static pciConfigPtr
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xf86GetPciHostConfigFromTag(PCITAG Tag)
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{
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int bus = PCI_BUS_FROM_TAG(Tag);
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pciBusInfo_t *pBusInfo;
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while ((bus < pciNumBuses) && (pBusInfo = pciBusInfo[bus])) {
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if (bus == pBusInfo->primary_bus)
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return pBusInfo->bridge;
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bus = pBusInfo->primary_bus;
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}
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return NULL; /* Bad data */
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}
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/*
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* This is ugly, but until I can extract this information from the kernel,
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* it'll have to do. The default I/O space size is 64K, and 4G for memory.
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* Anything else needs to go in this table. (PowerPC folk take note.)
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*
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* Note that Linux/SPARC userland is 32-bit, so 4G overflows to zero here.
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*
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* Please keep this table in ascending vendor/device order.
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*/
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static struct pciSizes {
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unsigned short vendor, device;
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unsigned long io_size, mem_size;
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} pciControllerSizes[] = {
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{
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PCI_VENDOR_SUN, PCI_CHIP_PSYCHO,
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1U << 16, 1U << 31
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},
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{
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PCI_VENDOR_SUN, PCI_CHIP_SCHIZO,
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1U << 24, 1U << 31 /* ??? */
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},
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{
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PCI_VENDOR_SUN, PCI_CHIP_SABRE,
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1U << 24, (unsigned long)(1ULL << 32)
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},
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{
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PCI_VENDOR_SUN, PCI_CHIP_HUMMINGBIRD,
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1U << 24, (unsigned long)(1ULL << 32)
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}
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};
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#define NUM_SIZES (sizeof(pciControllerSizes) / sizeof(pciControllerSizes[0]))
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static unsigned long
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linuxGetIOSize(PCITAG Tag)
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{
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pciConfigPtr pPCI;
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int i;
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/* Find host bridge */
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if ((pPCI = xf86GetPciHostConfigFromTag(Tag))) {
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/* Look up vendor/device */
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for (i = 0; i < NUM_SIZES; i++) {
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if (pPCI->pci_vendor > pciControllerSizes[i].vendor)
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continue;
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if (pPCI->pci_vendor < pciControllerSizes[i].vendor)
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break;
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if (pPCI->pci_device > pciControllerSizes[i].device)
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continue;
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if (pPCI->pci_device < pciControllerSizes[i].device)
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break;
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return pciControllerSizes[i].io_size;
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}
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}
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return 1U << 16; /* Default to 64K */
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}
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static void
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linuxGetSizes(PCITAG Tag, unsigned long *io_size, unsigned long *mem_size)
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{
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pciConfigPtr pPCI;
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int i;
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*io_size = (1U << 16); /* Default to 64K */
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*mem_size = (unsigned long)(1ULL << 32); /* Default to 4G */
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/* Find host bridge */
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if ((pPCI = xf86GetPciHostConfigFromTag(Tag))) {
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/* Look up vendor/device */
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for (i = 0; i < NUM_SIZES; i++) {
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if (pPCI->pci_vendor > pciControllerSizes[i].vendor)
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continue;
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if (pPCI->pci_vendor < pciControllerSizes[i].vendor)
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break;
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if (pPCI->pci_device > pciControllerSizes[i].device)
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continue;
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if (pPCI->pci_device < pciControllerSizes[i].device)
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break;
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*io_size = pciControllerSizes[i].io_size;
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*mem_size = pciControllerSizes[i].mem_size;
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break;
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}
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}
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}
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_X_EXPORT int
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xf86GetPciDomain(PCITAG Tag)
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{
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pciConfigPtr pPCI;
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int fd, result;
|
|
|
|
pPCI = xf86GetPciHostConfigFromTag(Tag);
|
|
|
|
if (pPCI && (result = PCI_DOM_FROM_BUS(pPCI->busnum)))
|
|
return result;
|
|
|
|
if (!pPCI || pPCI->fakeDevice)
|
|
return 1; /* Domain 0 is reserved */
|
|
|
|
if ((fd = linuxPciOpenFile(pPCI ? pPCI->tag : 0,FALSE)) < 0)
|
|
return 0;
|
|
|
|
if ((result = ioctl(fd, PCIIOC_CONTROLLER, 0)) < 0)
|
|
return 0;
|
|
|
|
return result + 1; /* Domain 0 is reserved */
|
|
}
|
|
|
|
static pointer
|
|
linuxMapPci(int ScreenNum, int Flags, PCITAG Tag,
|
|
ADDRESS Base, unsigned long Size, int mmap_ioctl)
|
|
{
|
|
do {
|
|
pciConfigPtr pPCI;
|
|
unsigned char *result;
|
|
ADDRESS realBase, Offset;
|
|
int fd, mmapflags, prot;
|
|
|
|
xf86InitVidMem();
|
|
|
|
pPCI = xf86GetPciHostConfigFromTag(Tag);
|
|
|
|
if (((fd = linuxPciOpenFile(pPCI ? pPCI->tag : 0,FALSE)) < 0) ||
|
|
(ioctl(fd, mmap_ioctl, 0) < 0))
|
|
break;
|
|
|
|
/* Note: IA-64 doesn't compile this and doesn't need to */
|
|
#ifdef __ia64__
|
|
|
|
# ifndef MAP_WRITECOMBINED
|
|
# define MAP_WRITECOMBINED 0x00010000
|
|
# endif
|
|
# ifndef MAP_NONCACHED
|
|
# define MAP_NONCACHED 0x00020000
|
|
# endif
|
|
|
|
if (Flags & VIDMEM_FRAMEBUFFER)
|
|
mmapflags = MAP_SHARED | MAP_WRITECOMBINED;
|
|
else
|
|
mmapflags = MAP_SHARED | MAP_NONCACHED;
|
|
|
|
#else /* !__ia64__ */
|
|
|
|
mmapflags = (Flags & VIDMEM_FRAMEBUFFER) / VIDMEM_FRAMEBUFFER;
|
|
|
|
if (ioctl(fd, PCIIOC_WRITE_COMBINE, mmapflags) < 0)
|
|
break;
|
|
|
|
mmapflags = MAP_SHARED;
|
|
|
|
#endif /* ?__ia64__ */
|
|
|
|
/* Align to page boundary */
|
|
realBase = Base & ~(getpagesize() - 1);
|
|
Offset = Base - realBase;
|
|
|
|
if (Flags & VIDMEM_READONLY)
|
|
prot = PROT_READ;
|
|
else
|
|
prot = PROT_READ | PROT_WRITE;
|
|
|
|
result = mmap(NULL, Size + Offset, prot, mmapflags, fd, realBase);
|
|
|
|
if (!result || ((pointer)result == MAP_FAILED))
|
|
return NULL;
|
|
|
|
xf86MakeNewMapping(ScreenNum, Flags, realBase, Size + Offset, result);
|
|
|
|
return result + Offset;
|
|
} while (0);
|
|
|
|
if (mmap_ioctl == PCIIOC_MMAP_IS_MEM)
|
|
return xf86MapVidMem(ScreenNum, Flags, Base, Size);
|
|
|
|
return NULL;
|
|
}
|
|
|
|
#define MAX_DOMAINS 257
|
|
static pointer DomainMmappedIO[MAX_DOMAINS];
|
|
static pointer DomainMmappedMem[MAX_DOMAINS];
|
|
|
|
static int
|
|
linuxOpenLegacy(PCITAG Tag, char *name)
|
|
{
|
|
#define PREFIX "/sys/class/pci_bus/%04x:%02x/%s"
|
|
char *path;
|
|
int domain, bus;
|
|
pciBusInfo_t *pBusInfo;
|
|
pciConfigPtr bridge = NULL;
|
|
int fd;
|
|
|
|
path = xalloc(strlen(PREFIX) + strlen(name));
|
|
if (!path)
|
|
return -1;
|
|
|
|
for (;;) {
|
|
domain = xf86GetPciDomain(Tag);
|
|
bus = PCI_BUS_NO_DOMAIN(PCI_BUS_FROM_TAG(Tag));
|
|
|
|
/* Domain 0 is reserved -- see xf86GetPciDomain() */
|
|
if ((domain <= 0) || (domain >= MAX_DOMAINS))
|
|
FatalError("linuxOpenLegacy(): domain out of range\n");
|
|
|
|
sprintf(path, PREFIX, domain - 1, bus, name);
|
|
fd = open(path, O_RDWR);
|
|
if (fd >= 0) {
|
|
xfree(path);
|
|
return fd;
|
|
}
|
|
|
|
pBusInfo = pciBusInfo[bus];
|
|
if (!pBusInfo || (bridge == pBusInfo->bridge) ||
|
|
!(bridge = pBusInfo->bridge)) {
|
|
xfree(path);
|
|
return -1;
|
|
}
|
|
|
|
Tag = bridge->tag;
|
|
}
|
|
|
|
xfree(path);
|
|
return fd;
|
|
}
|
|
|
|
/*
|
|
* xf86MapDomainMemory - memory map PCI domain memory
|
|
*
|
|
* This routine maps the memory region in the domain specified by Tag and
|
|
* returns a pointer to it. The pointer is saved for future use if it's in
|
|
* the legacy ISA memory space (memory in a domain between 0 and 1MB).
|
|
*/
|
|
_X_EXPORT pointer
|
|
xf86MapDomainMemory(int ScreenNum, int Flags, PCITAG Tag,
|
|
ADDRESS Base, unsigned long Size)
|
|
{
|
|
int domain = xf86GetPciDomain(Tag);
|
|
int fd;
|
|
|
|
/*
|
|
* We use /proc/bus/pci on non-legacy addresses or if the Linux sysfs
|
|
* legacy_mem interface is unavailable.
|
|
*/
|
|
if (Base > 1024*1024)
|
|
return linuxMapPci(ScreenNum, Flags, Tag, Base, Size,
|
|
PCIIOC_MMAP_IS_MEM);
|
|
|
|
if ((fd = linuxOpenLegacy(Tag, "legacy_mem")) < 0)
|
|
return linuxMapPci(ScreenNum, Flags, Tag, Base, Size,
|
|
PCIIOC_MMAP_IS_MEM);
|
|
|
|
|
|
/* If we haven't already mapped this legacy space, try to. */
|
|
if (!DomainMmappedMem[domain]) {
|
|
DomainMmappedMem[domain] = mmap(NULL, 1024*1024, PROT_READ|PROT_WRITE,
|
|
MAP_SHARED, fd, 0);
|
|
if (DomainMmappedMem[domain] == MAP_FAILED) {
|
|
close(fd);
|
|
perror("mmap failure");
|
|
FatalError("xf86MapDomainMem(): mmap() failure\n");
|
|
}
|
|
}
|
|
|
|
close(fd);
|
|
return (pointer)((char *)DomainMmappedMem[domain] + Base);
|
|
}
|
|
|
|
/*
|
|
* xf86MapDomainIO - map I/O space in this domain
|
|
*
|
|
* Each domain has a legacy ISA I/O space. This routine will try to
|
|
* map it using the Linux sysfs legacy_io interface. If that fails,
|
|
* it'll fall back to using /proc/bus/pci.
|
|
*
|
|
* If the legacy_io interface *does* exist, the file descriptor (fd below)
|
|
* will be saved in the DomainMmappedIO array in the upper bits of the
|
|
* pointer. Callers will do I/O with small port numbers (<64k values), so
|
|
* the platform I/O code can extract the port number and the fd, lseek to
|
|
* the port number in the legacy_io file, and issue the read or write.
|
|
*
|
|
* This has no means of returning failure, so all errors are fatal
|
|
*/
|
|
_X_EXPORT IOADDRESS
|
|
xf86MapDomainIO(int ScreenNum, int Flags, PCITAG Tag,
|
|
IOADDRESS Base, unsigned long Size)
|
|
{
|
|
int domain = xf86GetPciDomain(Tag);
|
|
int fd;
|
|
|
|
if ((domain <= 0) || (domain >= MAX_DOMAINS))
|
|
FatalError("xf86MapDomainIO(): domain out of range\n");
|
|
|
|
if (DomainMmappedIO[domain])
|
|
return (IOADDRESS)DomainMmappedIO[domain] + Base;
|
|
|
|
/* Permanently map all of I/O space */
|
|
if ((fd = linuxOpenLegacy(Tag, "legacy_io")) < 0) {
|
|
DomainMmappedIO[domain] = linuxMapPci(ScreenNum, Flags, Tag,
|
|
0, linuxGetIOSize(Tag),
|
|
PCIIOC_MMAP_IS_IO);
|
|
/* ia64 can't mmap legacy IO port space */
|
|
if (!DomainMmappedIO[domain])
|
|
return Base;
|
|
}
|
|
else { /* legacy_io file exists, encode fd */
|
|
DomainMmappedIO[domain] = (pointer)(fd << 24);
|
|
}
|
|
|
|
return (IOADDRESS)DomainMmappedIO[domain] + Base;
|
|
}
|
|
|
|
/*
|
|
* xf86ReadDomainMemory - copy from domain memory into a caller supplied buffer
|
|
*/
|
|
_X_EXPORT int
|
|
xf86ReadDomainMemory(PCITAG Tag, ADDRESS Base, int Len, unsigned char *Buf)
|
|
{
|
|
unsigned char *ptr, *src;
|
|
ADDRESS offset;
|
|
unsigned long size;
|
|
int len, pagemask = getpagesize() - 1;
|
|
|
|
unsigned int i, dom, bus, dev, func;
|
|
unsigned int fd;
|
|
char file[256];
|
|
struct stat st;
|
|
|
|
dom = PCI_DOM_FROM_TAG(Tag);
|
|
bus = PCI_BUS_FROM_TAG(Tag);
|
|
dev = PCI_DEV_FROM_TAG(Tag);
|
|
func = PCI_FUNC_FROM_TAG(Tag);
|
|
sprintf(file, "/sys/devices/pci%04x:%02x/%04x:%02x:%02x.%1x/rom",
|
|
dom, bus, dom, bus, dev, func);
|
|
|
|
/*
|
|
* If the caller wants the ROM and the sysfs rom interface exists,
|
|
* try to use it instead of reading it from /proc/bus/pci.
|
|
*/
|
|
if (((Base & 0xfffff) == 0xC0000) && (stat(file, &st) == 0)) {
|
|
if ((fd = open(file, O_RDWR)))
|
|
Base = 0x0;
|
|
|
|
/* enable the ROM first */
|
|
write(fd, "1", 2);
|
|
lseek(fd, 0, SEEK_SET);
|
|
|
|
/* copy the ROM until we hit Len, EOF or read error */
|
|
for (i = 0; i < Len && read(fd, Buf, 1) > 0; Buf++, i++)
|
|
;
|
|
|
|
write(fd, "0", 2);
|
|
close(fd);
|
|
|
|
return Len;
|
|
}
|
|
|
|
/* Ensure page boundaries */
|
|
offset = Base & ~pagemask;
|
|
size = ((Base + Len + pagemask) & ~pagemask) - offset;
|
|
|
|
ptr = xf86MapDomainMemory(-1, VIDMEM_READONLY, Tag, offset, size);
|
|
|
|
if (!ptr)
|
|
return -1;
|
|
|
|
/* Using memcpy() here can hang the system */
|
|
src = ptr + (Base - offset);
|
|
for (len = Len; len-- > 0;)
|
|
*Buf++ = *src++;
|
|
|
|
xf86UnMapVidMem(-1, ptr, size);
|
|
|
|
return Len;
|
|
}
|
|
|
|
resPtr
|
|
xf86BusAccWindowsFromOS(void)
|
|
{
|
|
pciConfigPtr *ppPCI, pPCI;
|
|
resPtr pRes = NULL;
|
|
resRange range;
|
|
unsigned long io_size, mem_size;
|
|
int domain;
|
|
|
|
if ((ppPCI = xf86scanpci(0))) {
|
|
for (; (pPCI = *ppPCI); ppPCI++) {
|
|
if ((pPCI->pci_base_class != PCI_CLASS_BRIDGE) ||
|
|
(pPCI->pci_sub_class != PCI_SUBCLASS_BRIDGE_HOST))
|
|
continue;
|
|
|
|
domain = xf86GetPciDomain(pPCI->tag);
|
|
linuxGetSizes(pPCI->tag, &io_size, &mem_size);
|
|
|
|
RANGE(range, 0, (ADDRESS)(mem_size - 1),
|
|
RANGE_TYPE(ResExcMemBlock, domain));
|
|
pRes = xf86AddResToList(pRes, &range, -1);
|
|
|
|
RANGE(range, 0, (IOADDRESS)(io_size - 1),
|
|
RANGE_TYPE(ResExcIoBlock, domain));
|
|
pRes = xf86AddResToList(pRes, &range, -1);
|
|
|
|
if (domain <= 0)
|
|
break;
|
|
}
|
|
}
|
|
|
|
return pRes;
|
|
}
|
|
|
|
resPtr
|
|
xf86PciBusAccWindowsFromOS(void)
|
|
{
|
|
pciConfigPtr *ppPCI, pPCI;
|
|
resPtr pRes = NULL;
|
|
resRange range;
|
|
unsigned long io_size, mem_size;
|
|
int domain;
|
|
|
|
if ((ppPCI = xf86scanpci(0))) {
|
|
for (; (pPCI = *ppPCI); ppPCI++) {
|
|
if ((pPCI->pci_base_class != PCI_CLASS_BRIDGE) ||
|
|
(pPCI->pci_sub_class != PCI_SUBCLASS_BRIDGE_HOST))
|
|
continue;
|
|
|
|
domain = xf86GetPciDomain(pPCI->tag);
|
|
linuxGetSizes(pPCI->tag, &io_size, &mem_size);
|
|
|
|
RANGE(range, 0, (ADDRESS)(mem_size - 1),
|
|
RANGE_TYPE(ResExcMemBlock, domain));
|
|
pRes = xf86AddResToList(pRes, &range, -1);
|
|
|
|
RANGE(range, 0, (IOADDRESS)(io_size - 1),
|
|
RANGE_TYPE(ResExcIoBlock, domain));
|
|
pRes = xf86AddResToList(pRes, &range, -1);
|
|
|
|
if (domain <= 0)
|
|
break;
|
|
}
|
|
}
|
|
|
|
return pRes;
|
|
}
|
|
|
|
|
|
resPtr
|
|
xf86AccResFromOS(resPtr pRes)
|
|
{
|
|
pciConfigPtr *ppPCI, pPCI;
|
|
resRange range;
|
|
unsigned long io_size, mem_size;
|
|
int domain;
|
|
|
|
if ((ppPCI = xf86scanpci(0))) {
|
|
for (; (pPCI = *ppPCI); ppPCI++) {
|
|
if ((pPCI->pci_base_class != PCI_CLASS_BRIDGE) ||
|
|
(pPCI->pci_sub_class != PCI_SUBCLASS_BRIDGE_HOST))
|
|
continue;
|
|
|
|
domain = xf86GetPciDomain(pPCI->tag);
|
|
linuxGetSizes(pPCI->tag, &io_size, &mem_size);
|
|
|
|
/*
|
|
* At minimum, the top and bottom resources must be claimed, so
|
|
* that resources that are (or appear to be) unallocated can be
|
|
* relocated.
|
|
*/
|
|
RANGE(range, 0x00000000u, 0x0009ffffu,
|
|
RANGE_TYPE(ResExcMemBlock, domain));
|
|
pRes = xf86AddResToList(pRes, &range, -1);
|
|
RANGE(range, 0x000c0000u, 0x000effffu,
|
|
RANGE_TYPE(ResExcMemBlock, domain));
|
|
pRes = xf86AddResToList(pRes, &range, -1);
|
|
RANGE(range, 0x000f0000u, 0x000fffffu,
|
|
RANGE_TYPE(ResExcMemBlock, domain));
|
|
pRes = xf86AddResToList(pRes, &range, -1);
|
|
|
|
RANGE(range, (ADDRESS)(mem_size - 1), (ADDRESS)(mem_size - 1),
|
|
RANGE_TYPE(ResExcMemBlock, domain));
|
|
pRes = xf86AddResToList(pRes, &range, -1);
|
|
|
|
RANGE(range, 0x00000000u, 0x00000000u,
|
|
RANGE_TYPE(ResExcIoBlock, domain));
|
|
pRes = xf86AddResToList(pRes, &range, -1);
|
|
RANGE(range, (IOADDRESS)(io_size - 1), (IOADDRESS)(io_size - 1),
|
|
RANGE_TYPE(ResExcIoBlock, domain));
|
|
pRes = xf86AddResToList(pRes, &range, -1);
|
|
|
|
if (domain <= 0)
|
|
break;
|
|
}
|
|
}
|
|
|
|
return pRes;
|
|
}
|
|
|
|
#endif /* !INCLUDE_XF86_NO_DOMAIN */
|
|
|
|
int linuxPciHandleBIOS(PCITAG Tag, int basereg, unsigned char *buf, int len)
|
|
{
|
|
unsigned int dom, bus, dev, func;
|
|
unsigned int fd;
|
|
char file[256];
|
|
struct stat st;
|
|
int ret;
|
|
int sofar = 0;
|
|
|
|
dom = PCI_DOM_FROM_TAG(Tag);
|
|
bus = PCI_BUS_FROM_TAG(Tag);
|
|
dev = PCI_DEV_FROM_TAG(Tag);
|
|
func = PCI_FUNC_FROM_TAG(Tag);
|
|
sprintf(file, "/sys/bus/pci/devices/%04x:%02x:%02x.%1x/rom",
|
|
dom, bus, dev, func);
|
|
|
|
if (stat(file, &st) == 0)
|
|
{
|
|
if ((fd = open(file, O_RDWR)))
|
|
basereg = 0x0;
|
|
|
|
/* enable the ROM first */
|
|
write(fd, "1", 2);
|
|
lseek(fd, 0, SEEK_SET);
|
|
do {
|
|
/* copy the ROM until we hit Len, EOF or read error */
|
|
ret = read(fd, buf+sofar, len-sofar);
|
|
if (ret <= 0)
|
|
break;
|
|
sofar += ret;
|
|
} while (sofar < len);
|
|
|
|
write(fd, "0", 2);
|
|
close(fd);
|
|
if (sofar < len)
|
|
xf86MsgVerb(X_INFO, 3, "Attempted to read BIOS %dKB from %s: got %dKB\n", len/1024, file, sofar/1024);
|
|
return sofar;
|
|
}
|
|
return 0;
|
|
}
|