516f452e78
chipsets can be probed without OS support as probing them is only
possible using ACPI. One example of this are the HP ZX1/2 chipsets:
previously the code assumed that these chips were present when no other
of the known chipsets could be probed. This assumption brought SGI
Altrix machines with 64 CPUs to a grinding halt.
467 lines
12 KiB
C
467 lines
12 KiB
C
/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/460gxPCI.c,v 1.4 2003/08/29 21:08:06 tsi Exp $ */
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/*
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* Copyright (C) 2002-2003 The XFree86 Project, Inc. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of the XFree86 Project shall
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* not be used in advertising or otherwise to promote the sale, use or other
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* dealings in this Software without prior written authorization from the
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* XFree86 Project.
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*/
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/*
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* This file contains the glue necessary for support of Intel's 460GX chipset.
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*/
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#include "460gxPCI.h"
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#include "xf86.h"
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#include "Pci.h"
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/* 460GX register definitions */
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/* SAC at 0:10:0 */
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#define CBN 0x0040
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/* SAC at CBN:0:0 */
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#define DEVNPRES 0x0070
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/* SAC at CBN:1[0-7]:0 */
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#define BUSNO 0x0048
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#define SUBNO 0x0049
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#define VGASE 0x0080
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#define PCIS 0x0084
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#define IOR 0x008C
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#define IORD 0x008E /* CBN:10:0 only */
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/* PXB at CBN:1[0-7]:1 */
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#define ERRCMD 0x0046
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static int cbn_460gx = -1;
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static CARD32 cbdevs_460gx = 0;
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static CARD16 iord_460gx;
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static int busno_460gx[8], subno_460gx[8];
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static CARD8 pcis_460gx[8], ior_460gx[8];
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static CARD8 has_err_460gx[8], err_460gx[8];
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static CARD8 iomap_460gx[16]; /* One for each 4k */
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static pciBusFuncs_t BusFuncs_460gx;
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static pciConfigPtr
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Verify460GXBus(int bus)
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{
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pciConfigPtr pPCI;
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if ((bus < 0) || (bus >= pciNumBuses) ||
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!pciBusInfo[bus] || !(pPCI = pciBusInfo[bus]->bridge) ||
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(pPCI->busnum != cbn_460gx) || (pPCI->funcnum != 0) ||
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(pPCI->devnum < 0x10) || (pPCI->devnum > 0x17))
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return NULL;
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return pPCI;
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}
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/*
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* This function is called to emulate the various settings in a P2P or CardBus
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* bridge's control register using one of a 460GX's SAC host bridges.
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*/
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static CARD16
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Control460GXBridge(int bus, CARD16 mask, CARD16 value)
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{
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pciConfigPtr pPCI;
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PCITAG tag;
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CARD16 current = 0;
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CARD8 tmp;
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if ((pPCI = Verify460GXBus(bus))) {
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/* Start with VGA enablement */
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tmp = pciReadByte(pPCI->tag, VGASE);
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if (tmp & 0x01) {
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current |= PCI_PCI_BRIDGE_VGA_EN;
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if ((mask & PCI_PCI_BRIDGE_VGA_EN) &&
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!(value & PCI_PCI_BRIDGE_VGA_EN))
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pciWriteByte(pPCI->tag, VGASE, tmp & ~0x01);
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} else {
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if (mask & value & PCI_PCI_BRIDGE_VGA_EN)
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pciWriteByte(pPCI->tag, VGASE, tmp | 0x01);
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}
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/* Move on to master abort failure enablement */
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if (has_err_460gx[pPCI->devnum - 0x10]) {
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tag = PCI_MAKE_TAG(pPCI->busnum, pPCI->devnum, pPCI->funcnum + 1);
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tmp = pciReadByte(tag, ERRCMD);
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if (tmp & 0x01) {
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current |= PCI_PCI_BRIDGE_MASTER_ABORT_EN;
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if ((mask & PCI_PCI_BRIDGE_MASTER_ABORT_EN) &&
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!(value & PCI_PCI_BRIDGE_MASTER_ABORT_EN))
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pciWriteByte(tag, ERRCMD, tmp & ~0x01);
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} else {
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if (mask & value & PCI_PCI_BRIDGE_MASTER_ABORT_EN)
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pciWriteByte(tag, ERRCMD, tmp | 0x01);
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}
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}
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/* Put emulation of any other P2P bridge control here */
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}
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return (current & ~mask) | (value & mask);
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}
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/*
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* Retrieve various bus numbers representing the connections provided by 460GX
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* host bridges.
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*/
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static void
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Get460GXBridgeBuses(int bus, int *primary, int *secondary, int *subordinate)
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{
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pciConfigPtr pPCI = Verify460GXBus(bus);
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int i;
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/* The returned bus numbers are initialised by the caller */
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if (!pPCI)
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return;
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i = pPCI->devnum - 0x10;
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/* These are not modified, so no need to re-read them */
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if (primary)
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*primary = pPCI->busnum;
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if (secondary)
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*secondary = busno_460gx[i];
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if (subordinate)
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*subordinate = subno_460gx[i];
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}
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/* Retrieves a list of the resources routed to a host bridge's secondary bus */
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static void
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Get460GXBridgeResources(int bus,
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pointer *ppIoRes,
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pointer *ppMemRes,
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pointer *ppPmemRes)
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{
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pciConfigPtr pPCI = Verify460GXBus(bus);
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resRange range;
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unsigned int i, j;
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if (ppIoRes) {
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xf86FreeResList(*ppIoRes);
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*ppIoRes = NULL;
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if (pPCI) {
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for (i = 0; i <= 0x0F; i++) {
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if (iomap_460gx[i] != pPCI->devnum)
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continue;
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RANGE(range, i << 12, ((i + 1) << 12) - 1,
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RANGE_TYPE(ResExcIoBlock, 0));
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*ppIoRes = xf86AddResToList(*ppIoRes, &range, -1);
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}
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}
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}
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if (ppMemRes) {
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xf86FreeResList(*ppMemRes);
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*ppMemRes = NULL;
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if (pPCI) {
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if (!(i = (pPCI->devnum - 0x10)))
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j = 127; /* (4GB - 32M) / 32M */
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else
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j = pcis_460gx[i - 1] & 0x7F;
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i = pcis_460gx[i] & 0x7F;
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if (i < j) {
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RANGE(range, i << 25, (j << 25) - 1,
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RANGE_TYPE(ResExcMemBlock, 0));
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*ppMemRes = xf86AddResToList(*ppMemRes, &range, -1);
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}
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}
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}
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if (ppPmemRes) {
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xf86FreeResList(*ppPmemRes);
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*ppPmemRes = NULL;
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}
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}
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/*
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* This checks for, and validates, the presence of the 460GX chipset, and sets
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* cbn_460gx to a positive value accordingly. This function returns TRUE if
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* the chipset scan is to be stopped, or FALSE if the scan is to move on to the
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* next chipset.
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*/
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Bool
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xorgProbe460GX(scanpciWrapperOpt flags)
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{
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pciBusInfo_t *pBusInfo;
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PCITAG tag;
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/* Bus zero should already be set up */
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if (!(pBusInfo = pciBusInfo[0])) {
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cbn_460gx = -1;
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return FALSE;
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}
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/* First look for a 460GX's primary host bridge */
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tag = PCI_MAKE_TAG(0, 0x10, 0);
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if (pciReadLong(tag, PCI_ID_REG) == DEVID(VENDOR_INTEL, CHIP_460GX_SAC)) {
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return TRUE;
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}
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cbn_460gx = -1;
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return FALSE;
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}
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void
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xf86PreScan460GX(void)
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{
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pciBusInfo_t *pBusInfo;
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PCITAG tag;
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CARD32 tmp;
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int i, devno;
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if (!(pBusInfo = pciBusInfo[0]))
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return;
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/* Get CBN (Chipset bus number) */
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tag = PCI_MAKE_TAG(0, 0x10, 0);
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if (!(cbn_460gx = (unsigned int)pciReadByte(tag, CBN))) {
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/* Sanity check failed */
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cbn_460gx = -1;
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return;
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}
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if (pciNumBuses <= cbn_460gx)
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pciNumBuses = cbn_460gx + 1;
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/* Set up bus CBN */
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if (!pciBusInfo[cbn_460gx]) {
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pciBusInfo[cbn_460gx] = xnfalloc(sizeof(pciBusInfo_t));
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*pciBusInfo[cbn_460gx] = *pBusInfo;
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}
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tag = PCI_MAKE_TAG(cbn_460gx, 0, 0);
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if (pciReadLong(tag, PCI_ID_REG) != DEVID(VENDOR_INTEL, CHIP_460GX_SAC)) {
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/* Sanity check failed */
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cbn_460gx = -1;
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return;
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}
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/*
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* Find out which CBN devices the firmware thinks are present. Of these,
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* we are only interested in devices 0x10 through 0x17.
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*/
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cbdevs_460gx = pciReadLong(tag, DEVNPRES);
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for (i = 0, devno = 0x10; devno <= 0x17; i++, devno++) {
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tag = PCI_MAKE_TAG(cbn_460gx, devno, 0);
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if (pciReadLong(tag, PCI_ID_REG) !=
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DEVID(VENDOR_INTEL, CHIP_460GX_SAC)) {
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/* Sanity check failed */
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cbn_460gx = -1;
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return;
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}
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if (devno == 0x10)
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iord_460gx = pciReadWord(tag, IORD);
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busno_460gx[i] = (unsigned int)pciReadByte(tag, BUSNO);
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subno_460gx[i] = (unsigned int)pciReadByte(tag, SUBNO);
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pcis_460gx[i] = pciReadByte(tag, PCIS);
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ior_460gx[i] = pciReadByte(tag, IOR);
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has_err_460gx[i] = err_460gx[i] = 0; /* Insurance */
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tag = PCI_MAKE_TAG(cbn_460gx, devno, 1);
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tmp = pciReadLong(tag, PCI_ID_REG);
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switch (tmp) {
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case DEVID(VENDOR_INTEL, CHIP_460GX_PXB):
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case DEVID(VENDOR_INTEL, CHIP_460GX_WXB):
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if (cbdevs_460gx & (1 << devno)) {
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/* Sanity check failed */
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cbn_460gx = -1;
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return;
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}
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/*
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* XXX I don't have WXB docs, but PCI register dumps indicate that
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* the registers we are interested in are consistent with those of
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* the PXB.
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*/
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err_460gx[i] = pciReadByte(tag, ERRCMD);
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has_err_460gx[i] = 1;
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break;
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case DEVID(VENDOR_INTEL, CHIP_460GX_GXB_1):
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if (cbdevs_460gx & (1 << devno)) {
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/* Sanity check failed */
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cbn_460gx = -1;
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return;
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}
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/*
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* XXX GXB isn't documented to have an ERRCMD register, nor any
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* other means of failing master aborts. For now, assume master
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* aborts are always allowed to complete normally.
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*/
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break;
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default:
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if (((CARD16)(tmp + 1U) <= (CARD16)1U) &&
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(cbdevs_460gx & (1U << devno)))
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break;
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/* Sanity check failed */
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cbn_460gx = -1;
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return;
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}
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}
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/* Allow master aborts to complete normally */
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for (i = 0, devno = 0x10; devno <= 0x17; i++, devno++) {
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if (!(err_460gx[i] & 0x01))
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continue;
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pciWriteByte(PCI_MAKE_TAG(cbn_460gx, devno, 1),
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ERRCMD, err_460gx[i] & ~0x01);
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}
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/*
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* The 460GX spec says that any access to buses higher than CBN will be
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* master-aborted. It seems possible however that this is not the case in
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* all 460GX implementations. For now, limit the bus scan to CBN, unless
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* we have already found a higher bus number.
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*/
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for (i = 0; subno_460gx[i] < cbn_460gx; ) {
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if (++i < 8)
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continue;
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pciMaxBusNum = cbn_460gx + 1;
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break;
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}
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return;
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}
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/* This does some 460GX-related processing after the PCI bus scan */
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void
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xf86PostScan460GX(void)
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{
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pciConfigPtr pPCI, *ppPCI;
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pciBusInfo_t *pBusInfo;
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int i, j, devno;
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if (cbn_460gx <= 0)
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return;
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/* Set up our extra bus functions */
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BusFuncs_460gx = *(pciBusInfo[0]->funcs);
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BusFuncs_460gx.pciControlBridge = Control460GXBridge;
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BusFuncs_460gx.pciGetBridgeBuses = Get460GXBridgeBuses;
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BusFuncs_460gx.pciGetBridgeResources = Get460GXBridgeResources;
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/*
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* Mark all host bridges so that they are ignored by the upper-level
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* xf86GetPciBridgeInfo() function. This marking is later clobbered by the
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* tail end of xf86scanpci() for those bridges that actually have bus
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* segments associated with them.
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*/
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ppPCI = xf86scanpci(0); /* Recursion is only apparent */
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while ((pPCI = *ppPCI++)) {
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if ((pPCI->pci_base_class == PCI_CLASS_BRIDGE) &&
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(pPCI->pci_sub_class == PCI_SUBCLASS_BRIDGE_HOST))
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pPCI->businfo = HOST_NO_BUS;
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}
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ppPCI = xf86scanpci(0); /* Recursion is only apparent */
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j = 0;
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/*
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* Fix up CBN bus linkage. This is somewhat arbitrary. The bridge chosen
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* for this must be a CBN device so that bus CBN can be recognised as the
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* root segment. It also cannot be any of the bus expanders (devices
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* CBN:0x10:0 through CBN:0x17:0 nor any of their functions). For now, we
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* chose the SAC host bridge at CBN:0:0.
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*/
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pBusInfo = pciBusInfo[cbn_460gx];
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pBusInfo->bridge = pciBusInfo[0]->bridge; /* Just in case */
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while ((pPCI = *ppPCI++)) {
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if (pPCI->busnum < cbn_460gx)
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continue;
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if (pPCI->busnum > cbn_460gx)
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break;
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if (pPCI->devnum < 0)
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continue;
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if (pPCI->devnum > 0)
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break;
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if (pPCI->funcnum < 0)
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continue;
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if (pPCI->funcnum > 0)
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break;
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pBusInfo->bridge = pPCI;
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pBusInfo->secondary = FALSE;
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pBusInfo->primary_bus = cbn_460gx;
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break;
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}
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for (i = 0, devno = 0x10; devno <= 0x17; i++, devno++) {
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/* Restore ERRCMD registers */
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if (err_460gx[i] & 0x01)
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pciWriteByte(PCI_MAKE_TAG(cbn_460gx, devno, 1),
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ERRCMD, err_460gx[i]);
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if (!(cbdevs_460gx & (1 << devno))) {
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while ((pPCI = *ppPCI++)) {
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if (pPCI->busnum < cbn_460gx)
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continue;
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if (pPCI->busnum > cbn_460gx)
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break;
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if (pPCI->devnum < devno)
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continue;
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if (pPCI->devnum > devno)
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break;
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if (pPCI->funcnum < 0)
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continue;
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if (pPCI->funcnum > 0)
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break;
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if ((pBusInfo = pciBusInfo[busno_460gx[i]]))
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break;
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/* Fix bus linkage */
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pBusInfo->bridge = pPCI;
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pBusInfo->secondary = TRUE;
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pBusInfo->primary_bus = cbn_460gx;
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/* Plug in chipset routines */
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pBusInfo->funcs = &BusFuncs_460gx;
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break;
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}
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}
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/* Decode IOR registers */
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for(; j <= (ior_460gx[i] & 0x0F); j++)
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iomap_460gx[j] = devno;
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}
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/* The bottom 4k of I/O space is always routed to PCI0a */
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iomap_460gx[0] = 0x10;
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/* Decode IORD register */
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for (j = 1; j <= 0x0F; j++)
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if (iord_460gx & (1 << j))
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iomap_460gx[j] = 0x10;
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}
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