969 lines
19 KiB
C
969 lines
19 KiB
C
/*
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* $XFree86$
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*
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* Copyright © 2000 Keith Packard
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that
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* copyright notice and this permission notice appear in supporting
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* documentation, and that the name of Keith Packard not be used in
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* advertising or publicity pertaining to distribution of the software without
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* specific, written prior permission. Keith Packard makes no
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* representations about the suitability of this software for any purpose. It
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* is provided "as is" without express or implied warranty.
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*
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* KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "igsreg.h"
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#include <stdio.h>
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#define CR00 IGS_CR+0x00
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#define CR01 IGS_CR+0x01
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#define CR02 IGS_CR+0x02
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#define CR03 IGS_CR+0x03
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#define CR04 IGS_CR+0x04
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#define CR05 IGS_CR+0x05
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#define CR06 IGS_CR+0x06
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#define CR07 IGS_CR+0x07
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#define CR08 IGS_CR+0x08
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#define CR09 IGS_CR+0x09
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#define CR0A IGS_CR+0x0A
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#define CR0B IGS_CR+0x0B
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#define CR0C IGS_CR+0x0C
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#define CR0D IGS_CR+0x0D
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#define CR0E IGS_CR+0x0E
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#define CR0F IGS_CR+0x0F
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#define CR10 IGS_CR+0x10
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#define CR11 IGS_CR+0x11
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#define CR12 IGS_CR+0x12
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#define CR13 IGS_CR+0x13
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#define CR14 IGS_CR+0x14
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#define CR15 IGS_CR+0x15
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#define CR16 IGS_CR+0x16
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#define CR17 IGS_CR+0x17
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#define CR18 IGS_CR+0x18
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#define CR19 IGS_CR+0x19
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#define CR1A IGS_CR+0x1A
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#define CR1B IGS_CR+0x1B
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#define CR1C IGS_CR+0x1C
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#define CR1D IGS_CR+0x1D
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#define CR1E IGS_CR+0x1E
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#define CR1F IGS_CR+0x1F
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#define CR20 IGS_CR+0x20
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#define CR21 IGS_CR+0x21
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#define CR22 IGS_CR+0x22
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#define CR23 IGS_CR+0x23
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#define CR24 IGS_CR+0x24
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#define CR25 IGS_CR+0x25
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#define CR26 IGS_CR+0x26
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#define CR27 IGS_CR+0x27
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#define CR28 IGS_CR+0x28
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#define CR29 IGS_CR+0x29
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#define CR2A IGS_CR+0x2A
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#define CR2B IGS_CR+0x2B
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#define CR2C IGS_CR+0x2C
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#define CR2D IGS_CR+0x2D
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#define CR2E IGS_CR+0x2E
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#define CR2F IGS_CR+0x2F
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#define CR30 IGS_CR+0x30
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#define CR31 IGS_CR+0x31
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#define CR32 IGS_CR+0x32
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#define CR33 IGS_CR+0x33
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#define CR34 IGS_CR+0x34
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#define CR35 IGS_CR+0x35
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#define CR36 IGS_CR+0x36
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#define CR37 IGS_CR+0x37
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#define CR38 IGS_CR+0x38
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#define CR39 IGS_CR+0x39
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#define CR3A IGS_CR+0x3A
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#define CR3B IGS_CR+0x3B
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#define CR3C IGS_CR+0x3C
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#define CR3D IGS_CR+0x3D
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#define CR3E IGS_CR+0x3E
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#define CR3F IGS_CR+0x3F
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#define CR40 IGS_CR+0x40
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#define CR41 IGS_CR+0x41
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#define CR42 IGS_CR+0x42
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#define CR43 IGS_CR+0x43
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#define CR44 IGS_CR+0x44
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#define CR45 IGS_CR+0x45
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#define CR46 IGS_CR+0x46
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#define CR47 IGS_CR+0x47
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#define CR48 IGS_CR+0x48
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#define CR_FIRST CR00
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#define CR_LAST CR48
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#define SR00 IGS_SR+0x00
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#define SR01 IGS_SR+0x01
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#define SR02 IGS_SR+0x02
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#define SR03 IGS_SR+0x03
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#define SR04 IGS_SR+0x04
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#define SR_FIRST SR00
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#define SR_LAST SR04
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#define AR00 IGS_AR+0x00
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#define AR01 IGS_AR+0x01
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#define AR02 IGS_AR+0x02
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#define AR03 IGS_AR+0x03
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#define AR04 IGS_AR+0x04
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#define AR05 IGS_AR+0x05
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#define AR06 IGS_AR+0x06
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#define AR07 IGS_AR+0x07
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#define AR08 IGS_AR+0x08
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#define AR09 IGS_AR+0x09
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#define AR0A IGS_AR+0x0A
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#define AR0B IGS_AR+0x0B
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#define AR0C IGS_AR+0x0C
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#define AR0D IGS_AR+0x0D
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#define AR0E IGS_AR+0x0E
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#define AR0F IGS_AR+0x0F
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#define AR10 IGS_AR+0x10
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#define AR11 IGS_AR+0x11
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#define AR12 IGS_AR+0x12
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#define AR13 IGS_AR+0x13
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#define AR14 IGS_AR+0x14
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#define AR_FIRST AR00
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#define AR_LAST AR14
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#define GR00 IGS_GR+0x00
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#define GR01 IGS_GR+0x01
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#define GR02 IGS_GR+0x02
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#define GR03 IGS_GR+0x03
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#define GR04 IGS_GR+0x04
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#define GR05 IGS_GR+0x05
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#define GR06 IGS_GR+0x06
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#define GR07 IGS_GR+0x07
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#define GR08 IGS_GR+0x08
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#define GR09 IGS_GR+0x09
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#define GR0A IGS_GR+0x0A
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#define GR0B IGS_GR+0x0B
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#define GR0C IGS_GR+0x0C
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#define GR0D IGS_GR+0x0D
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#define GR0E IGS_GR+0x0E
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#define GR0F IGS_GR+0x0F
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#define GR10 IGS_GR+0x10
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#define GR11 IGS_GR+0x11
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#define GR12 IGS_GR+0x12
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#define GR13 IGS_GR+0x13
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#define GR14 IGS_GR+0x14
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#define GR15 IGS_GR+0x15
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#define GR16 IGS_GR+0x16
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#define GR17 IGS_GR+0x17
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#define GR18 IGS_GR+0x18
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#define GR19 IGS_GR+0x19
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#define GR1A IGS_GR+0x1A
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#define GR1B IGS_GR+0x1B
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#define GR1C IGS_GR+0x1C
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#define GR1D IGS_GR+0x1D
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#define GR1E IGS_GR+0x1E
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#define GR1F IGS_GR+0x1F
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#define GR20 IGS_GR+0x20
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#define GR21 IGS_GR+0x21
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#define GR22 IGS_GR+0x22
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#define GR23 IGS_GR+0x23
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#define GR24 IGS_GR+0x24
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#define GR25 IGS_GR+0x25
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#define GR26 IGS_GR+0x26
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#define GR27 IGS_GR+0x27
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#define GR28 IGS_GR+0x28
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#define GR29 IGS_GR+0x29
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#define GR2A IGS_GR+0x2A
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#define GR2B IGS_GR+0x2B
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#define GR2C IGS_GR+0x2C
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#define GR2D IGS_GR+0x2D
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#define GR2E IGS_GR+0x2E
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#define GR2F IGS_GR+0x2F
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#define GR30 IGS_GR+0x30
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#define GR31 IGS_GR+0x31
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#define GR32 IGS_GR+0x32
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#define GR33 IGS_GR+0x33
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#define GR34 IGS_GR+0x34
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#define GR35 IGS_GR+0x35
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#define GR36 IGS_GR+0x36
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#define GR37 IGS_GR+0x37
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#define GR38 IGS_GR+0x38
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#define GR39 IGS_GR+0x39
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#define GR3A IGS_GR+0x3A
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#define GR3B IGS_GR+0x3B
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#define GR3C IGS_GR+0x3C
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#define GR3D IGS_GR+0x3D
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#define GR3E IGS_GR+0x3E
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#define GR3F IGS_GR+0x3F
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#define GR40 IGS_GR+0x40
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#define GR41 IGS_GR+0x41
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#define GR42 IGS_GR+0x42
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#define GR43 IGS_GR+0x43
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#define GR44 IGS_GR+0x44
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#define GR45 IGS_GR+0x45
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#define GR46 IGS_GR+0x46
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#define GR47 IGS_GR+0x47
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#define GR48 IGS_GR+0x48
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#define GR49 IGS_GR+0x49
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#define GR4A IGS_GR+0x4A
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#define GR4B IGS_GR+0x4B
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#define GR4C IGS_GR+0x4C
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#define GR4D IGS_GR+0x4D
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#define GR4E IGS_GR+0x4E
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#define GR4F IGS_GR+0x4F
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#define GR50 IGS_GR+0x50
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#define GR51 IGS_GR+0x51
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#define GR52 IGS_GR+0x52
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#define GR53 IGS_GR+0x53
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#define GR54 IGS_GR+0x54
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#define GR55 IGS_GR+0x55
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#define GR56 IGS_GR+0x56
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#define GR57 IGS_GR+0x57
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#define GR58 IGS_GR+0x58
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#define GR59 IGS_GR+0x59
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#define GR5A IGS_GR+0x5A
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#define GR5B IGS_GR+0x5B
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#define GR5C IGS_GR+0x5C
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#define GR5D IGS_GR+0x5D
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#define GR5E IGS_GR+0x5E
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#define GR5F IGS_GR+0x5F
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#define GR60 IGS_GR+0x60
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#define GR61 IGS_GR+0x61
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#define GR62 IGS_GR+0x62
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#define GR63 IGS_GR+0x63
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#define GR64 IGS_GR+0x64
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#define GR65 IGS_GR+0x65
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#define GR66 IGS_GR+0x66
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#define GR67 IGS_GR+0x67
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#define GR68 IGS_GR+0x68
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#define GR69 IGS_GR+0x69
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#define GR6A IGS_GR+0x6A
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#define GR6B IGS_GR+0x6B
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#define GR6C IGS_GR+0x6C
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#define GR6D IGS_GR+0x6D
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#define GR6E IGS_GR+0x6E
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#define GR6F IGS_GR+0x6F
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#define GR70 IGS_GR+0x70
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#define GR71 IGS_GR+0x71
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#define GR72 IGS_GR+0x72
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#define GR73 IGS_GR+0x73
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#define GR74 IGS_GR+0x74
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#define GR75 IGS_GR+0x75
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#define GR76 IGS_GR+0x76
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#define GR77 IGS_GR+0x77
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#define GR78 IGS_GR+0x78
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#define GR79 IGS_GR+0x79
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#define GR7A IGS_GR+0x7A
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#define GR7B IGS_GR+0x7B
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#define GR7C IGS_GR+0x7C
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#define GR7D IGS_GR+0x7D
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#define GR7E IGS_GR+0x7E
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#define GR7F IGS_GR+0x7F
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#define GR80 IGS_GR+0x80
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#define GR81 IGS_GR+0x81
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#define GR82 IGS_GR+0x82
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#define GR83 IGS_GR+0x83
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#define GR84 IGS_GR+0x84
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#define GR85 IGS_GR+0x85
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#define GR86 IGS_GR+0x86
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#define GR87 IGS_GR+0x87
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#define GR88 IGS_GR+0x88
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#define GR89 IGS_GR+0x89
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#define GR8A IGS_GR+0x8A
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#define GR8B IGS_GR+0x8B
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#define GR8C IGS_GR+0x8C
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#define GR8D IGS_GR+0x8D
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#define GR8E IGS_GR+0x8E
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#define GR8F IGS_GR+0x8F
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#define GR90 IGS_GR+0x90
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#define GR91 IGS_GR+0x91
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#define GR92 IGS_GR+0x92
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#define GR93 IGS_GR+0x93
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#define GR94 IGS_GR+0x94
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#define GR95 IGS_GR+0x95
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#define GR96 IGS_GR+0x96
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#define GR97 IGS_GR+0x97
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#define GR98 IGS_GR+0x98
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#define GR99 IGS_GR+0x99
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#define GR9A IGS_GR+0x9A
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#define GR9B IGS_GR+0x9B
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#define GR9C IGS_GR+0x9C
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#define GR9D IGS_GR+0x9D
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#define GR9E IGS_GR+0x9E
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#define GR9F IGS_GR+0x9F
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#define GRA0 IGS_GR+0xA0
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#define GRA1 IGS_GR+0xA1
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#define GRA2 IGS_GR+0xA2
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#define GRA3 IGS_GR+0xA3
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#define GRA4 IGS_GR+0xA4
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#define GRA5 IGS_GR+0xA5
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#define GRA6 IGS_GR+0xA6
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#define GRA7 IGS_GR+0xA7
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#define GRA8 IGS_GR+0xA8
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#define GRA9 IGS_GR+0xA9
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#define GRAA IGS_GR+0xAA
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#define GRAB IGS_GR+0xAB
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#define GRAC IGS_GR+0xAC
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#define GRAD IGS_GR+0xAD
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#define GRAE IGS_GR+0xAE
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#define GRAF IGS_GR+0xAF
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#define GRB0 IGS_GR+0xB0
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#define GRB1 IGS_GR+0xB1
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#define GRB2 IGS_GR+0xB2
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#define GRB3 IGS_GR+0xB3
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#define GRB4 IGS_GR+0xB4
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#define GRB5 IGS_GR+0xB5
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#define GRB6 IGS_GR+0xB6
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#define GRB7 IGS_GR+0xB7
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#define GRB8 IGS_GR+0xB8
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#define GRB9 IGS_GR+0xB9
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#define GRBA IGS_GR+0xBA
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#define GRBB IGS_GR+0xBB
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#define GRBC IGS_GR+0xBC
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#define GRBD IGS_GR+0xBD
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#define GRBE IGS_GR+0xBE
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#define GRBF IGS_GR+0xBF
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#define GR_FIRST GR00
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#define GR_LAST GRBF
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#define GREX3C IGS_GREX+(0x3c-IGS_GREXBASE)
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VgaReg igs_h_total[] = {
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CR00, 0, 8,
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VGA_REG_END
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};
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VgaReg igs_h_de_end[] = {
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CR01, 0, 8,
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VGA_REG_END
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};
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VgaReg igs_h_bstart[] = {
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CR02, 0, 8,
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VGA_REG_END
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};
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VgaReg igs_h_bend[] = {
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CR03, 0, 5,
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CR05, 7, 1,
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VGA_REG_END
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};
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VgaReg igs_de_skew[] = {
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CR03, 5, 2,
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VGA_REG_END
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};
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VgaReg igs_ena_vr_access[] = {
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CR03, 7, 1,
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VGA_REG_END
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};
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VgaReg igs_h_rstart[] = {
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CR04, 0, 8,
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VGA_REG_END
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};
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VgaReg igs_h_rend[] = {
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CR05, 0, 5,
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VGA_REG_END
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};
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VgaReg igs_h_rdelay[] = {
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CR05, 5, 2,
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VGA_REG_END
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};
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VgaReg igs_v_total[] = {
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CR06, 0, 8,
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CR07, 0, 1,
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CR07, 5, 1,
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GR11, 0, 1,
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VGA_REG_END
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};
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VgaReg igs_v_rstart[] = {
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CR10, 0, 8,
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CR07, 2, 1,
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CR07, 7, 1,
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GR11, 2, 1,
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VGA_REG_END
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};
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VgaReg igs_v_rend[] = {
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CR11, 0, 4,
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VGA_REG_END
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};
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VgaReg igs_clear_v_int[] = {
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CR11, 4, 1,
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VGA_REG_END
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};
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VgaReg igs_disable_v_int[] = {
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CR11, 5, 1,
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VGA_REG_END
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};
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VgaReg igs_bandwidth[] = {
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CR11, 6, 1,
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VGA_REG_END
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};
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VgaReg igs_crt_protect[] = {
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CR11, 7, 1,
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VGA_REG_END
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};
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VgaReg igs_v_de_end[] = {
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CR12, 0, 8,
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CR07, 1, 1,
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CR07, 6, 1,
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GR11, 1, 1,
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VGA_REG_END
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};
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VgaReg igs_offset[] = {
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CR13, 0, 8,
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GR15, 4, 2,
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VGA_REG_END
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};
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VgaReg igs_v_bstart[] = {
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CR15, 0, 8,
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CR07, 3, 1,
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CR09, 5, 1,
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GR11, 3, 1,
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VGA_REG_END
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};
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VgaReg igs_v_bend[] = {
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|
CR16, 0, 7,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_linecomp[] = {
|
|
CR18, 0, 8,
|
|
CR07, 4, 1,
|
|
CR09, 6, 1,
|
|
GR11, 4, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_ivideo[] = {
|
|
GR11, 5, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_num_fetch[] = {
|
|
GR14, 0, 8,
|
|
GR15, 0, 2,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_wcrt0[] = {
|
|
CR1F, 0, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_wcrt1[] = {
|
|
CR1F, 1, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_rcrts1[] = {
|
|
CR1F, 4, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_selwk[] = {
|
|
CR1F, 6, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_dot_clock_8[] = {
|
|
SR01, 0, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_screen_off[] = {
|
|
SR01, 5, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_enable_write_plane[] = {
|
|
SR02, 0, 4,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_mexhsyn[] = {
|
|
GR16, 0, 2,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_mexvsyn[] = {
|
|
GR16, 2, 2,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_pci_burst_write[] = {
|
|
GR30, 5, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_pci_burst_read[] = {
|
|
GR30, 7, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_iow_retry[] = {
|
|
GREX3C, 0, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_mw_retry[] = {
|
|
GREX3C, 1, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_mr_retry[] = {
|
|
GREX3C, 2, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
|
|
|
|
VgaReg igs_biga22en[] = {
|
|
GR3D, 4, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_biga24en[] = {
|
|
GR3D, 5, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_biga22force[] = {
|
|
GR3D, 6, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_bigswap[] = {
|
|
GR3F, 0, 6,
|
|
VGA_REG_END
|
|
};
|
|
|
|
/* #define IGS_BIGSWAP_8 0x3f */
|
|
/* #define IGS_BIGSWAP_16 0x2a */
|
|
/* #define IGS_BIGSWAP_32 0x00 */
|
|
|
|
VgaReg igs_sprite_x[] = {
|
|
GR50, 0, 8,
|
|
GR51, 0, 3,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_sprite_preset_x[] = {
|
|
GR52, 0, 6,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_sprite_y[] = {
|
|
GR53, 0, 8,
|
|
GR54, 0, 3,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_sprite_preset_y[] = {
|
|
GR55, 0, 6,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_sprite_visible[] = {
|
|
GR56, 0, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_sprite_64x64[] = {
|
|
GR56, 1, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_mgrext[] = {
|
|
GR57, 0, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_hcshf[] = {
|
|
GR57, 4, 2,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_mbpfix[] = {
|
|
GR57, 6, 2,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_overscan_red[] = {
|
|
GR58, 0, 8,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_overscan_green[] = {
|
|
GR59, 0, 8,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_overscan_blue[] = {
|
|
GR5A, 0, 8,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_memgopg[] = {
|
|
GR73, 2, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_memr2wpg[] = {
|
|
GR73, 1, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_crtff16[] = {
|
|
GR73, 3, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_fifomust[] = {
|
|
GR74, 0, 5,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_fifogen[] = {
|
|
GR75, 0, 5,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_mode_sel[] = {
|
|
GR77, 0, 4,
|
|
VGA_REG_END
|
|
};
|
|
|
|
/* #define IGS_MODE_TEXT 0 */
|
|
/* #define IGS_MODE_8 1 */
|
|
/* #define IGS_MODE_565 2 */
|
|
/* #define IGS_MODE_5551 6 */
|
|
/* #define IGS_MODE_8888 3 */
|
|
/* #define IGS_MODE_888 4 */
|
|
/* #define IGS_MODE_332 9 */
|
|
/* #define IGS_MODE_4444 10 */
|
|
|
|
VgaReg igs_sprite_addr[] = {
|
|
GR7E, 0, 8,
|
|
GR7F, 0, 4,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_fastmpie[] = {
|
|
GR9E, 0, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_vclk_m[] = {
|
|
GRB0, 0, 8,
|
|
GRBA, 0, 3,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_vclk_n[] = {
|
|
GRB1, 0, 5,
|
|
GRBA, 3, 3,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_vfsel[] = {
|
|
GRB1, 5, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_vclk_p[] = {
|
|
GRB1, 6, 2,
|
|
GRBA, 6, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_frqlat[] = {
|
|
GRB9, 7, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
|
|
VgaReg igs_dac_mask[] = {
|
|
IGS_DAC + 0, 0, 8,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_dac_read_index[] = {
|
|
IGS_DAC + 1, 0, 8,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_dac_write_index[] = {
|
|
IGS_DAC + 2, 0, 8,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_dac_data[] = {
|
|
IGS_DAC + 3, 0, 8,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_rampwdn[] = {
|
|
IGS_DACEX + 0, 0, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_dac6_8[] = {
|
|
IGS_DACEX + 0, 1, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_ramdacbypass[] = {
|
|
IGS_DACEX + 0, 4, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_dacpwdn[] = {
|
|
IGS_DACEX + 0, 6, 1,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_cursor_read_index[] = {
|
|
IGS_DACEX + 1, 0, 8,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_cursor_write_index[] = {
|
|
IGS_DACEX + 2, 0, 8,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VgaReg igs_cursor_data[] = {
|
|
IGS_DACEX + 3, 0, 8,
|
|
VGA_REG_END
|
|
};
|
|
|
|
VGA8
|
|
_igsInb (VgaCard *card, VGA16 port)
|
|
{
|
|
VGAVOL8 *reg;
|
|
|
|
if (card->closure)
|
|
return VgaReadMemb ((VGA32) card->closure + port);
|
|
else
|
|
return VgaInb (port);
|
|
}
|
|
|
|
void
|
|
_igsOutb (VgaCard *card, VGA8 value, VGA16 port)
|
|
{
|
|
if (card->closure)
|
|
VgaWriteMemb (value, (VGA32) card->closure + port);
|
|
else
|
|
VgaOutb (value, port);
|
|
}
|
|
|
|
void
|
|
_igsRegMap (VgaCard *card, VGA16 reg, VgaMap *map, VGABOOL write)
|
|
{
|
|
if (reg < IGS_SR + IGS_NSR)
|
|
{
|
|
map->access = VgaAccessIndIo;
|
|
map->port = 0x3c4;
|
|
map->addr = 0;
|
|
map->value = 1;
|
|
map->index = reg - IGS_SR;
|
|
}
|
|
else if (reg < IGS_GR + IGS_NGR)
|
|
{
|
|
map->access = VgaAccessIndIo;
|
|
map->port = 0x3ce;
|
|
map->addr = 0;
|
|
map->value = 1;
|
|
map->index = reg - IGS_GR;
|
|
}
|
|
else if (reg < IGS_GREX + IGS_NGREX)
|
|
{
|
|
VGA8 gr33;
|
|
|
|
map->access = VgaAccessDone;
|
|
_igsOutb (card, 0x33, 0x3ce);
|
|
gr33 = _igsInb (card, 0x3cf);
|
|
_igsOutb (card, gr33 | 0x40, 0x3cf);
|
|
_igsOutb (card, IGS_GREXBASE + reg - IGS_GREX, 0x3ce);
|
|
if (write)
|
|
_igsOutb (card, map->value, 0x3cf);
|
|
else
|
|
map->value = _igsInb (card, 0x3cf);
|
|
_igsOutb (card, 0x33, 0x3ce);
|
|
_igsOutb (card, gr33, 0x3cf);
|
|
return;
|
|
}
|
|
else if (reg < IGS_AR + IGS_NAR)
|
|
{
|
|
reg -= IGS_AR;
|
|
map->access = VgaAccessDone;
|
|
/* reset AFF to index */
|
|
(void) _igsInb (card, 0x3da);
|
|
if (reg >= 16)
|
|
reg |= 0x20;
|
|
_igsOutb (card, reg, 0x3c0);
|
|
if (write)
|
|
_igsOutb (card, map->value, 0x3c0);
|
|
else
|
|
map->value = _igsInb (card, 0x3c1);
|
|
if (!(reg & 0x20))
|
|
{
|
|
/* enable video display again */
|
|
(void) _igsInb (card, 0x3da);
|
|
_igsOutb (card, 0x20, 0x3c0);
|
|
}
|
|
return;
|
|
}
|
|
else if (reg < IGS_CR + IGS_NCR)
|
|
{
|
|
map->access = VgaAccessIndIo;
|
|
map->port = 0x3d4;
|
|
map->addr = 0;
|
|
map->value = 1;
|
|
map->index = reg - IGS_CR;
|
|
}
|
|
else if (reg < IGS_DAC + IGS_NDAC)
|
|
{
|
|
map->access = VgaAccessIo;
|
|
map->port = 0x3c6 + reg - IGS_DAC;
|
|
}
|
|
else if (reg < IGS_DACEX + IGS_NDACEX)
|
|
{
|
|
VGA8 gr56;
|
|
reg = 0x3c6 + reg - IGS_DACEX;
|
|
map->access = VgaAccessDone;
|
|
_igsOutb (card, 0x56, 0x3ce);
|
|
gr56 = _igsInb (card, 0x3cf);
|
|
_igsOutb (card, gr56 | 4, 0x3cf);
|
|
if (write)
|
|
_igsOutb (card, map->value, reg);
|
|
else
|
|
map->value = _igsInb (card, reg);
|
|
_igsOutb (card, gr56, 0x3cf);
|
|
return;
|
|
}
|
|
else switch (reg) {
|
|
case IGS_MISC_OUT:
|
|
map->access = VgaAccessIo;
|
|
if (write)
|
|
map->port = 0x3c2;
|
|
else
|
|
map->port = 0x3cc;
|
|
break;
|
|
case IGS_INPUT_STATUS_1:
|
|
map->access = VgaAccessIo;
|
|
map->port = 0x3da;
|
|
break;
|
|
}
|
|
if (card->closure)
|
|
{
|
|
map->port = map->port + (VGA32) card->closure;
|
|
if (map->access == VgaAccessIo)
|
|
map->access = VgaAccessMem;
|
|
if (map->access == VgaAccessIndIo)
|
|
map->access = VgaAccessIndMem;
|
|
}
|
|
}
|
|
|
|
VgaSave igsSaves[] = {
|
|
CR00, CR18,
|
|
SR01, SR02,
|
|
GR11, GRBA,
|
|
IGS_MISC_OUT, IGS_MISC_OUT,
|
|
VGA_SAVE_END
|
|
};
|
|
|
|
void
|
|
igsRegInit (IgsVga *igsvga, VGAVOL8 *mmio)
|
|
{
|
|
igsvga->card.map = _igsRegMap;
|
|
igsvga->card.closure = (void *) mmio;
|
|
igsvga->card.max = IGS_NREG;
|
|
igsvga->card.values = igsvga->values;
|
|
igsvga->card.saves = igsSaves;
|
|
}
|
|
|
|
void
|
|
igsSave (IgsVga *igsvga)
|
|
{
|
|
igsSetImm (igsvga, igs_wcrt0, 1);
|
|
igsSetImm (igsvga, igs_wcrt1, 1);
|
|
igsSetImm (igsvga, igs_rcrts1, 1);
|
|
igsSetImm (igsvga, igs_selwk, 1);
|
|
VgaPreserve (&igsvga->card);
|
|
}
|
|
|
|
void
|
|
igsReset (IgsVga *igsvga)
|
|
{
|
|
VgaRestore (&igsvga->card);
|
|
igsSetImm (igsvga, igs_frqlat, 0);
|
|
igsSetImm (igsvga, igs_frqlat, 1);
|
|
igsSetImm (igsvga, igs_frqlat, 0);
|
|
VgaFinish (&igsvga->card);
|
|
}
|
|
|
|
char *
|
|
igsRegName(char *buf, VGA16 reg)
|
|
{
|
|
if (reg < IGS_SR + IGS_NSR)
|
|
{
|
|
sprintf (buf, " SR%02X", reg - IGS_SR);
|
|
}
|
|
else if (reg < IGS_GR + IGS_NGR)
|
|
{
|
|
sprintf (buf, " GR%02X", reg - IGS_GR);
|
|
}
|
|
else if (reg < IGS_GREX + IGS_NGREX)
|
|
{
|
|
sprintf (buf, " GRX%02X", reg - IGS_GREX + IGS_GREXBASE);
|
|
}
|
|
else if (reg < IGS_AR + IGS_NAR)
|
|
{
|
|
sprintf (buf, " AR%02X", reg - IGS_AR);
|
|
}
|
|
else if (reg < IGS_CR + IGS_NCR)
|
|
{
|
|
sprintf (buf, " CR%02X", reg - IGS_CR);
|
|
}
|
|
else if (reg < IGS_DAC + IGS_NDAC)
|
|
{
|
|
sprintf (buf, " DAC%02X", reg - IGS_DAC);
|
|
}
|
|
else if (reg < IGS_DACEX + IGS_NDACEX)
|
|
{
|
|
sprintf (buf, "DACX%02X", reg - IGS_DACEX);
|
|
}
|
|
else switch (reg) {
|
|
case IGS_MISC_OUT:
|
|
sprintf (buf, "MISC_O");
|
|
break;
|
|
case IGS_INPUT_STATUS_1:
|
|
sprintf (buf, "IN_S_1");
|
|
break;
|
|
}
|
|
return buf;
|
|
}
|