369 lines
19 KiB
PHP
369 lines
19 KiB
PHP
;++
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; Copyright (c) 1992, 1993 Wyse Technology
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;
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; Module Name:
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;
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; wy7000mp.inc
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;
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; Abstract:
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;
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; Wyse 7000i MP include file
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;
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; Author:
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; John Nels Fuller (o-johnf) 3-Apr-1992
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;--
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;*****************************
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; Wyse 7000i MP defines
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;
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WyModel740 Equ 00170335Fh ;EISA id for model 740 system board
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WyModel760 Equ 00178335Fh ;EISA id for model 760 system board
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WyModel780 Equ 00978335Fh ;EISA id for model 780 system board
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; ;(model hasn't been named, but
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; ; 780 is as good as anything)
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WyUPcpu Equ 00171335Fh ;EISA id for UP-cpu (can only be
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; read through EISA_ReadId)
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WyMPcpu Equ 00179335Fh ;EISA id for MP-cpu (can only be
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; read through EISA_ReadId)
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WyIDmask Equ 00FFFFFFFh ;mask out rev/speed for cpu id
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WyShadowArea Equ 0000F0000h ;physical address of BIOS RAM shadow
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WyShadowLength Equ 000010000h ;length of BIOS RAM shadow (64Kb)
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WarmResetVector Equ 000000467h ;address of low mem reset variable
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EISA_Functions Equ 00000F859h ;offset into BIOS of EISA Int 15h
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EISA_ReadId Equ 00000D884h ;function to read EISA slot ID
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MPFW_FuncTable Equ 0FFFE0100h ;physical address of F/W function table
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fnICU_Sync_Mstr Equ 25h ;function number of F/W routine to
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; cause specified cpu's to sync and
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; report back (used to verify that
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; installed cpu's are running)
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fnICU_Send_Mstr Equ 23h ;function number of F/W routine to
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; send command/data packtets to other
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; cpu's (cpu's must be running in
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; F/W or Diag as at boot time).
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fnOS_Diag_Mon Equ 0Dh ;function number of O/S transfer
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; to Diagnostic monitor
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fnOS_Panic Equ 0Ch ;function number of O/S transfer
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; to Diagnostic monitor for NMI/crash
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; panic
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; These four reigisters access the bus control unit chip (BCU) for the
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; Wyse Wyde Bus(tm) (WWB), CpuIntCmd and CpuPriortyLevel are read only
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; except for the local cpu (i.e. My+CpuIntCmt and My+CpuPriortyLevel).
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CpuPtrReg Equ 0800h ;cpu pointer register (add WWB slot*16)
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CpuDataReg Equ 0804h ;cpu data register (add WWB slot*16)
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CpuIntCmd Equ 0802h ;cpu interrupt cmd reg (add WWB slot*16)
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CpuPriortyLevel Equ 0806h ;cpu int priority level (add WWB slot*16)
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; These two registers access the cache control unit chip (CCU)
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; (80486 mp-cpu's only)
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CpuCCUptr Equ 0C00h ;CCU pointer register (add WWB slot*16)
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CpuCCUdata Equ 0C02h ;CCU data register (add WWB slot*16)
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; These three registers access the three Wyde Bus Interface chips (WBI)
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; (80486 mp-cpu's only)
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CpuWBIlow Equ 0C04h ;low WBI register (add WWB slot*16)
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CpuWBIhigh Equ 0C06h ;high WBI register (add WWB slot*16)
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CpuWBIaddr Equ 0C08h ;addr WBI register (add WWB slot*16)
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; These two registers access the WWB Data Controller chip (WDC)
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; (Pentium cpu's only) (DON'T add WWB slot*16 to these addresses)
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MyCpuWDCptr Equ 0CF0h ;WDC pointer register
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MyCpuWDCdata Equ 0CF2h ;WDC data register
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; These two registers access the WWB Data Path chip (WDP)
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; (Pentium cpu's only) (DON'T add WWB slot*16 to these addresses)
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MyCpuWDPlow Equ 0CF4h ;low WDP register
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MyCpuWDPhigh Equ 0CF6h ;high WDP register
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; Each cpu has a 16450 uart connected to the diagnostic serial port
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; on the back of the machine, only one cpu's 16450 is enabled (normally
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; processor 0) so the WWB slot for that cpu must be used for other
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; cpu's to access it. However, not all variations of cpu boards
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; support access to this uart from another cpu.
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CpuDiagUart Equ 0808h ;16450 base address (add WWB slot*16)
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; Use these fixed WWB slots numbers for modifing above i/o addresses
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My Equ 00F0h ;WWB slot number specifies local cpu
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Sys Equ 0000h ;WWB slot number for system board
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; use for 760/780 system board only
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; and only for BCU/ICU registers
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;
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; The following registers are accessed by writing the register number
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; to CpuPtrReg and then reading or writing the 16-bit data at CpuDataReg
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; each 16-bit access to CpuDataReg toggles bit 1 of CpuPtrReg so, for
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; example to access both ICU_IMR0 and ICU_IMR1 write ICU_IMR0 to
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; CpuPtrReg and do two 16-bit i/o's to CpuDataReg to access first the
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; low word and then the high word of the mask register.
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;
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ICU_SYS_CPU Equ 00h ;system cpu config register
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ICU_CPU_MASTER Equ 04h ;system cpu master register
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ICU_CPU_SYNC Equ 08h ;cpu synchronization register
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BCU_STAT0 Equ 0Ch ;BCU status register 0
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PERR_LOW Equ 02h ;parity error, low 32-bits of data bus
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PERR_HIGH Equ 04h ;parity error, high 32-bits of data bus
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PERR_ADDR Equ 08h ;parity error, address bus
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PERR_CCU Equ 10h ;cache control unit error
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PERR_TAG Equ 20h ;snoop tag parity error
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NOT_FAIL Equ 80h ;when zero red LED on CPU is on
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CPU_STAT Equ 10h ;CPU status register
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BCU_ID Equ 14h ;Slot identification (bits 0-3)
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WWB_ID_MASK Equ 0Fh ;these bits are WWB slot number
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BCU_GPR Equ 18h ;General purpose register
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BCU_BCTLR Equ 1Ch ;BCU control register
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A20M_WWB Equ 01h ;when set gate A20 comes from 8042
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A20M_CPU Equ 02h ;when set forces A20 to be masked
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SLOW_ENB Equ 04h ;when set allows CPUSlowDown from
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; EISA chipset to drive CPU Hold
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; (for 8Mhz emulation)
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SNP_ENB Equ 08h ;when set the cache snoops bus cycles
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BCU_FWT Equ 10h ;when set two extra clocks are inserted
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; in cache line operations
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BCU_ERRCTLR Equ 20h ;BCU error control register
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ERR_MODE Equ 03h ;error mode field mask
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ERR_MODE0 Equ 00h ;report no errors
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ERR_MODE1 Equ 01h ;Local CPU gets NMI (only local CPU
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; can see this)
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ERR_MODE2 Equ 02h ;report to WWB NMI line (all CPU's
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; may see this)
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ERR_MODE3 Equ 03h ;report on WWB PCHK line (all CPU's
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; and ISP may see this, ISP may assert
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; WWB NMI in response)
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NMI_ENB Equ 04h ;enable NMI's to CPU
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WWB_NMI Equ 08h ;enable WWB NMI to cause NMI this CPU
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WWB_PCHK Equ 10h ;enable WWB PCHK to cause NMI this CPU
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BCU_STAT1 Equ 24h ;BCU status register 1
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NMISRC_WWB Equ 01h ;NMI source is WWB NMI
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NMISRC_PCHK Equ 02h ;NMI source is WWB PCHK
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NMISRC_BTO Equ 04h ;NMI source is WWB bus timeout
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NMISRC_EXT Equ 08h ;NMI source is NMI button on CPU
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NMISRC_ICU Equ 10h ;NMI source is ICU (send NMI to Slot)
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ICU_DATA Equ 40h ;ICU data register
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ICU_ICTLR Equ 44h ;ICU control register
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WWB_INT Equ 01h ;specifies this ICU to be master
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IACK_MODE Equ 02h ;set for MP interrupt mode
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ICU_AEOI Equ 04h ;automatic EOI for ICU interrupts
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INT_ENB Equ 08h ;enable interrupts from ICU
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TMR_TEST Equ 10h ;select timer test mode
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IVP_TEST Equ 40h ;select Int Vector Processor test mode
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MSK_CPURST Equ 80h ;set to prevent 8042 from reseting cpu
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ICU_IMR0 Equ 48h ;ICU int mask register (low 16 bits)
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ICU_IMR1 Equ 4Ah ;ICU int mask register (high 16 bits)
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IMR_MASK Equ 007FFFFFh ;only bits 0-22 are valid
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ICU_MSKPND0 Equ 4Ch ;ICU masked pending register (low)
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ICU_MSKPND1 Equ 4Eh ;ICU masked pending register (high)
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ICU_VB0 Equ 50h ;vector base register 0
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ICU_VB1 Equ 54h ;vector base register 1
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ICU_VB2 Equ 58h ;vector base register 2
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ICU_STAT Equ 5Ch ;ICU status register
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INSERV0 Equ 01h ;int in service bit 0
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INSERV1 Equ 02h ;int in service bit 1
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ICU_PSR0 Equ 60h ;pending status register (low)
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ICU_PSR1 Equ 62h ;pending status register (high)
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ICU_CNT_VAL Equ 64h ;timer count current value
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ICU_CNT_REG Equ 68h ;timer count register
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ICU_LIPTR Equ 6Ch ;local interrupt ptr register
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;each field specifies the Local/IPI
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;interrupt level of a local bus intr.
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;with 0 meaning the intr. is disabled
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;Each Local/IPI int level maps to a
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;specific CpuPriorityLevel (CPL)--see
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;chart in WYIRQL.ASM. CPL is also the
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;bit # in ICU_IMR to mask the level.
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lipSlot Equ 7000h ;mask for slot IPI interrupt
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lipSlotShl Equ 12 ;shift for slot IPI interrupt field
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lipSlotVal Equ 1 Shl lipSlotShl ;IPI level used by this Hal
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lipSlotCPL Equ 1 ;CPL / IMR bit number
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lipGlobal Equ 0700h ;mask for global IPI interrupt
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lipGlobalShl Equ 8 ;shift for global IPI interrupt field
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lipGlobalVal Equ 3 Shl lipGlobalShl ;IPI level used by this Hal
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lipGlobalCPL Equ 3 ;CPL / IMR bit number
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lipSerial Equ 0070h ;mask for diagnostic uart interrupt
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lipSerialShl Equ 4 ;shift for uart interrupt field
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lipSerialVal Equ (lipGlobalVal Shr lipGlobalShl) Shl lipSerialShl
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;use same as Global
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lipSerialCPL Equ lipGlobalCPL ;CPL / IMR bit number
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lipTimer Equ 0007h ;mask for local timer interrupt
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lipTimerShl Equ 0 ;shift for timer interrupt field
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lipTimerVal Equ 2 Shl lipTimerShl ;IPI level used by this Hal
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lipTimerCPL Equ 2 ;CPL / IMR bit number
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lipDefault Equ lipSlotVal+lipTimerVal+lipSerialVal+0 ;Global off
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ICU_CNTREC Equ 70h ;recovery count register
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ICU_VIN Equ 74h ;vector in register
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ICU_VOUT Equ 78h ;vector out register
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SYS_WBI_LOW Equ 0F0h ;low WBI register (system board only)
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SYS_WBI_HIGH Equ 0F4h ;high WBI register (system board only)
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SYS_WBI_ADDR Equ 0F8h ;addr WBI register (system board only)
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;
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; The following describes the CpuIntCmd register
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;
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ICU_CMD_BUSY Equ 0100h ;do not issue command while set
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ICU_IPI_SLOT Equ 0060h ;IPI cpu in slot (add WWB slot number)
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ICU_CLR_INSERV0 Equ 00E8h ;clear interrupt in service bit 0
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ICU_CLR_INSERV1 Equ 00E9h ;clear interrupt in service bit 1
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ICU_XMT_INT_SND Equ 0020h ;rebroadcast int (add CPL of int)
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;(cannot be used for CLOCK2/IPI)
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ICU_XMT_GLB_INT Equ 00E0h ;Send global interrupt
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;
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; The following describes each WBI register
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;
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WBI_SLT_MSK Equ 000Fh ;WWB slot number
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WBI_FPAR_ERR Equ 0010h ;force parity error for diagnostics
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WBI_IACK_MODE Equ 0020h ;set for MP interrupt acknowlege mode
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WBI_FWT Equ 0040h ;force 2 clock cycles on Cpu bus
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; Equ 0080h ;reserved
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WBI_PE_IN_0 Equ 0100h ;for data WBI's:
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; parity err in 1st inbound data phase
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;for addr WBI:
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; parity err in inbound address
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WBI_PE_IN_1 Equ 0200h ;for data WBI's:
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; parity err in 2nd inboud data phase
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;for addr WBI:
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; parity err in inbound address
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WBI_PE_OUT_CPU Equ 0400h ;data parity err outbound data from cpu
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WBI_PE_OUT_CSH Equ 0800h ;data perr outbound data from cache
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WBI_PE_BYTE0 Equ 1000h ;parity error in byte lane 0
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WBI_PE_BYTE1 Equ 2000h ;parity error in byte lane 1
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WBI_PE_BYTE2 Equ 4000h ;parity error in byte lane 2
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WBI_PE_BYTE3 Equ 8000h ;parity error in byte lane 3
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; The following describes the bits in the WDP register that concern HAL
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;
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WDP_IACK_MODE Equ 0020h ;set for MP interrupt acknowlege mode
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WDP_FPE_EN Equ 0040h ;enable CPU FERR onto WWB (to IRQ13)
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;
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; The following registers are accessed by writing the register number
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; to CpuCCUptr and then reading or writing the 16-bit data at CpuCCUdata.
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;
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CCU_CR Equ 00h ;CCU control register
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CACHE_EN Equ 0001h ;enable secondary cache
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BURST_EN Equ 0002h ;enable CPU burst cycles
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WWB_FPE_EN Equ 0004h ;enable CPU FERR onto WWB (to IRQ13)
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;(reset to use int 10h trap for
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; floating point errors, thus
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; preventing IRQ13's for FP err)
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TPEN Equ 0008h ;cache tag parity enable
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SHADOW_ROM_EN Equ 0010h ;enable BIOS ROM shadow in 1st Mb
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AMOD Equ 0020h ;enable local memory mapped I/O to
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; cache data/tags for diagnostics,
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; flash rom write area, diagnostic
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; ROM area.
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SRAM_MODE Equ 0040h ;specifies type of SRAM used for
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; cache, standard/~synchronous
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SYSCONFIG Equ 0080h ;allows configuration cycles to be
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; run on WWB
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PCD_EN Equ 0100h ;enables use of cpu PCD output
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RDWT Equ 0200h ;adds one wait cycle to reads
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WRWT_MSK Equ 0C00h ;mask for write wait cycle count field
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BRWT Equ 1000h ;adds one wiat state on cpu burst reads
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FST_ODD Equ 2000h ;force odd parity on cache state bits
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; for diagnostics
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FTAG_ODD Equ 4000h ;force odd parity on cache tag bits
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; for diagnostics
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CCU_FWT Equ 8000h ;force two clocks for cache-WBI data
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; transfers (cache fill, copy back,
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; intervention, & snoop update)
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CCU_ERR0 Equ 18h ;CCU latched error status register 0
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TPAR Equ 0001h ;tag parity bit
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SNP_ERR Equ 0002h ;snoop error
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TAG_DATA Equ 1FFCh ;tag data bits
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CCU_STATE Equ 6000h ;cache line state bits:
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; 0=default, 1=exclusive, 2=shared
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; 3=modified
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SPAR Equ 8000h ;state parity bit
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CCU_ERR1 Equ 1Ah ;CCU latched error status register 1
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TAGINDEX Equ 3FFFh ;tag index address
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CPU_DPE Equ 4000h ;cpu data parity error
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VALID_ERROR Equ 8000h ;set when CCU_ERR0,1 have valid info
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CCU_ID Equ 1Ch ;CCU has WWB slot number
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;*****************************
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; end of list
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;
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; The kernel leaves some space (64 byte) of the PCR for the HAL to use
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; as it needs. Currently this space is used for some efficiency in
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; some of the MP specific code and is highly implementation
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; dependant.
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;
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PcHalData struc
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; pchStallCnt dd ? ;per processor stall count
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pchCurLiptr dd ? ;per processor current ICU_LIPTR
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pchPrNum db ? ;NT's processor number
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pchPrSlot db ? ;WWB processor slot
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pchPentiumFlag db ? ;non-zero if current cpu is a Pentium
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pchHwIrql db ? ;Irql to which CpuPriorityLevel is
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;programmed. Due to lazy Irql's this
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;may be different than PcIrql
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PcHalData ends
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cr equ 0ah
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lf equ 0dh
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PIC1_BASE equ PRIMARY_VECTOR_BASE
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PIC2_BASE equ PRIMARY_VECTOR_BASE + 8
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IPIv_BASE equ PRIMARY_VECTOR_BASE + 16
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PIC_SLAVE_IRQ equ 2
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IFDEF STD_CALL
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enproc macro pn
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if DBG
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%out enproc pn
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ifndef _ProcSub@4
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extrn _ProcSub@4:NEAR
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endif ;_ProcSub
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push pn ;save routine number
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call _ProcSub@4 ;write to BCU_GPR
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endif ;DBG
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endm
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exproc macro pn
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if DBG
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%out exproc pn
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push (pn) or 80h ;save routine number and exit flag
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call _ProcSub@4 ;write to BCU_GPR
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endif ;DBG
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endm
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ELSE
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enproc macro pn
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if DBG
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%out enproc pn
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ifndef _ProcSub
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extrn _ProcSub:NEAR
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endif ;_ProcSub
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push pn ;save routine number
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call _ProcSub ;write to BCU_GPR
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lea esp, [esp][4] ;remove parameter w/o altering flags
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endif ;DBG
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endm
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exproc macro pn
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if DBG
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%out exproc pn
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push (pn) or 80h ;save routine number and exit flag
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call _ProcSub ;write to BCU_GPR
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lea esp, [esp][4] ;remove parameter w/o altering flags
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endif ;DBG
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endm
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ENDIF
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