2016-05-24 08:35:23 +02:00
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// Copyright (c) 2011-present, Facebook, Inc. All rights reserved.
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2017-07-16 01:03:42 +02:00
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// This source code is licensed under both the GPLv2 (found in the
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// COPYING file in the root directory) and Apache 2.0 License
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// (found in the LICENSE.Apache file in the root directory).
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2016-05-24 08:35:23 +02:00
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#include "rocksdb/utilities/sim_cache.h"
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2021-01-29 07:08:46 +01:00
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2016-05-24 08:35:23 +02:00
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#include <atomic>
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2021-01-29 07:08:46 +01:00
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2019-09-16 19:31:27 +02:00
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#include "file/writable_file_writer.h"
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2017-04-06 04:02:00 +02:00
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#include "monitoring/statistics.h"
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2016-07-21 00:28:04 +02:00
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#include "port/port.h"
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2017-07-28 21:18:09 +02:00
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#include "rocksdb/env.h"
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2021-01-29 07:08:46 +01:00
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#include "rocksdb/file_system.h"
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2017-07-28 21:18:09 +02:00
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#include "util/mutexlock.h"
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#include "util/string_util.h"
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2016-05-24 08:35:23 +02:00
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2020-02-20 21:07:53 +01:00
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namespace ROCKSDB_NAMESPACE {
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2016-05-24 08:35:23 +02:00
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namespace {
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2017-07-28 21:18:09 +02:00
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class CacheActivityLogger {
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public:
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CacheActivityLogger()
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: activity_logging_enabled_(false), max_logging_size_(0) {}
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~CacheActivityLogger() {
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MutexLock l(&mutex_);
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StopLoggingInternal();
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2020-08-25 01:41:42 +02:00
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bg_status_.PermitUncheckedError();
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2017-07-28 21:18:09 +02:00
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}
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Status StartLogging(const std::string& activity_log_file, Env* env,
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uint64_t max_logging_size = 0) {
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assert(activity_log_file != "");
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assert(env != nullptr);
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Status status;
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2021-01-29 07:08:46 +01:00
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FileOptions file_opts;
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2017-07-28 21:18:09 +02:00
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MutexLock l(&mutex_);
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// Stop existing logging if any
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StopLoggingInternal();
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// Open log file
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2021-01-29 07:08:46 +01:00
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status = WritableFileWriter::Create(env->GetFileSystem(), activity_log_file,
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file_opts, &file_writer_, nullptr);
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2017-07-28 21:18:09 +02:00
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if (!status.ok()) {
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return status;
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}
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max_logging_size_ = max_logging_size;
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activity_logging_enabled_.store(true);
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return status;
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}
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void StopLogging() {
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MutexLock l(&mutex_);
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StopLoggingInternal();
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}
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void ReportLookup(const Slice& key) {
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if (activity_logging_enabled_.load() == false) {
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return;
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}
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std::string log_line = "LOOKUP - " + key.ToString(true) + "\n";
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// line format: "LOOKUP - <KEY>"
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MutexLock l(&mutex_);
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Status s = file_writer_->Append(log_line);
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if (!s.ok() && bg_status_.ok()) {
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bg_status_ = s;
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}
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if (MaxLoggingSizeReached() || !bg_status_.ok()) {
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// Stop logging if we have reached the max file size or
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// encountered an error
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StopLoggingInternal();
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}
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}
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void ReportAdd(const Slice& key, size_t size) {
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if (activity_logging_enabled_.load() == false) {
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return;
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}
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std::string log_line = "ADD - ";
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log_line += key.ToString(true);
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log_line += " - ";
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AppendNumberTo(&log_line, size);
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2020-04-20 20:37:36 +02:00
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log_line += "\n";
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2017-07-28 21:18:09 +02:00
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// line format: "ADD - <KEY> - <KEY-SIZE>"
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MutexLock l(&mutex_);
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Status s = file_writer_->Append(log_line);
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if (!s.ok() && bg_status_.ok()) {
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bg_status_ = s;
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}
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if (MaxLoggingSizeReached() || !bg_status_.ok()) {
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// Stop logging if we have reached the max file size or
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// encountered an error
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StopLoggingInternal();
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}
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}
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Status& bg_status() {
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MutexLock l(&mutex_);
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return bg_status_;
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}
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private:
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bool MaxLoggingSizeReached() {
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mutex_.AssertHeld();
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return (max_logging_size_ > 0 &&
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file_writer_->GetFileSize() >= max_logging_size_);
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}
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void StopLoggingInternal() {
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mutex_.AssertHeld();
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if (!activity_logging_enabled_) {
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return;
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}
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activity_logging_enabled_.store(false);
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Status s = file_writer_->Close();
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if (!s.ok() && bg_status_.ok()) {
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bg_status_ = s;
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}
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}
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// Mutex to sync writes to file_writer, and all following
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// class data members
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port::Mutex mutex_;
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// Indicates if logging is currently enabled
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// atomic to allow reads without mutex
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std::atomic<bool> activity_logging_enabled_;
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// When reached, we will stop logging and close the file
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// Value of 0 means unlimited
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uint64_t max_logging_size_;
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std::unique_ptr<WritableFileWriter> file_writer_;
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Status bg_status_;
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};
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2016-05-24 08:35:23 +02:00
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// SimCacheImpl definition
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class SimCacheImpl : public SimCache {
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public:
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// capacity for real cache (ShardedLRUCache)
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// test_capacity for key only cache
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Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
2019-06-18 01:33:40 +02:00
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SimCacheImpl(std::shared_ptr<Cache> sim_cache, std::shared_ptr<Cache> cache)
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2016-05-24 08:35:23 +02:00
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: cache_(cache),
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Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
2019-06-18 01:33:40 +02:00
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key_only_cache_(sim_cache),
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2016-08-11 02:42:24 +02:00
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miss_times_(0),
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2017-11-28 22:15:20 +01:00
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hit_times_(0),
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stats_(nullptr) {}
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2016-05-24 08:35:23 +02:00
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2019-02-14 22:52:47 +01:00
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~SimCacheImpl() override {}
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void SetCapacity(size_t capacity) override { cache_->SetCapacity(capacity); }
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2016-05-24 08:35:23 +02:00
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2019-02-14 22:52:47 +01:00
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void SetStrictCapacityLimit(bool strict_capacity_limit) override {
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2016-05-24 08:35:23 +02:00
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cache_->SetStrictCapacityLimit(strict_capacity_limit);
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}
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2021-05-14 07:57:51 +02:00
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using Cache::Insert;
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2020-04-01 01:09:11 +02:00
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Status Insert(const Slice& key, void* value, size_t charge,
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void (*deleter)(const Slice& key, void* value), Handle** handle,
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Priority priority) override {
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2016-05-24 08:35:23 +02:00
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// The handle and value passed in are for real cache, so we pass nullptr
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2020-04-01 01:09:11 +02:00
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// to key_only_cache_ for both instead. Also, the deleter function pointer
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// will be called by user to perform some external operation which should
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// be applied only once. Thus key_only_cache accepts an empty function.
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// *Lambda function without capture can be assgined to a function pointer
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2016-05-24 08:35:23 +02:00
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Handle* h = key_only_cache_->Lookup(key);
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if (h == nullptr) {
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2020-08-25 01:41:42 +02:00
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// TODO: Check for error here?
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auto s = key_only_cache_->Insert(
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key, nullptr, charge, [](const Slice& /*k*/, void* /*v*/) {}, nullptr,
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priority);
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s.PermitUncheckedError();
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2016-05-24 08:35:23 +02:00
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} else {
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key_only_cache_->Release(h);
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}
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2017-07-28 21:18:09 +02:00
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cache_activity_logger_.ReportAdd(key, charge);
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Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
2019-06-18 01:33:40 +02:00
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if (!cache_) {
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return Status::OK();
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}
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2016-08-20 01:43:31 +02:00
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return cache_->Insert(key, value, charge, deleter, handle, priority);
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2016-05-24 08:35:23 +02:00
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}
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2021-05-14 07:57:51 +02:00
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using Cache::Lookup;
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2019-02-14 22:52:47 +01:00
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Handle* Lookup(const Slice& key, Statistics* stats) override {
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2016-05-24 08:35:23 +02:00
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Handle* h = key_only_cache_->Lookup(key);
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if (h != nullptr) {
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key_only_cache_->Release(h);
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inc_hit_counter();
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2016-09-01 22:50:39 +02:00
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RecordTick(stats, SIM_BLOCK_CACHE_HIT);
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2016-08-11 02:42:24 +02:00
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} else {
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inc_miss_counter();
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2016-09-01 22:50:39 +02:00
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RecordTick(stats, SIM_BLOCK_CACHE_MISS);
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2016-05-24 08:35:23 +02:00
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}
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2017-07-28 21:18:09 +02:00
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cache_activity_logger_.ReportLookup(key);
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Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
2019-06-18 01:33:40 +02:00
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if (!cache_) {
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return nullptr;
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}
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2016-09-01 22:50:39 +02:00
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return cache_->Lookup(key, stats);
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2016-05-24 08:35:23 +02:00
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}
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2019-02-14 22:52:47 +01:00
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bool Ref(Handle* handle) override { return cache_->Ref(handle); }
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2017-01-11 01:48:23 +01:00
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2021-05-14 07:57:51 +02:00
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using Cache::Release;
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2019-02-14 22:52:47 +01:00
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bool Release(Handle* handle, bool force_erase = false) override {
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2017-04-24 20:21:47 +02:00
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return cache_->Release(handle, force_erase);
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}
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2016-05-24 08:35:23 +02:00
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2019-02-14 22:52:47 +01:00
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void Erase(const Slice& key) override {
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2016-05-24 08:35:23 +02:00
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cache_->Erase(key);
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key_only_cache_->Erase(key);
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}
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2019-02-14 22:52:47 +01:00
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void* Value(Handle* handle) override { return cache_->Value(handle); }
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2016-05-24 08:35:23 +02:00
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2019-02-14 22:52:47 +01:00
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uint64_t NewId() override { return cache_->NewId(); }
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2016-05-24 08:35:23 +02:00
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2019-02-14 22:52:47 +01:00
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size_t GetCapacity() const override { return cache_->GetCapacity(); }
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2016-05-24 08:35:23 +02:00
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2019-02-14 22:52:47 +01:00
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bool HasStrictCapacityLimit() const override {
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2016-05-24 08:35:23 +02:00
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return cache_->HasStrictCapacityLimit();
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}
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2019-02-14 22:52:47 +01:00
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size_t GetUsage() const override { return cache_->GetUsage(); }
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2016-05-24 08:35:23 +02:00
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2019-02-14 22:52:47 +01:00
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size_t GetUsage(Handle* handle) const override {
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2016-07-15 19:41:36 +02:00
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return cache_->GetUsage(handle);
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2016-05-24 08:35:23 +02:00
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}
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2019-09-20 21:00:55 +02:00
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size_t GetCharge(Handle* handle) const override {
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return cache_->GetCharge(handle);
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}
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2019-06-19 02:32:44 +02:00
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2019-02-14 22:52:47 +01:00
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size_t GetPinnedUsage() const override { return cache_->GetPinnedUsage(); }
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2016-05-24 08:35:23 +02:00
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2019-02-14 22:52:47 +01:00
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void DisownData() override {
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2016-05-24 08:35:23 +02:00
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cache_->DisownData();
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key_only_cache_->DisownData();
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}
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2019-02-14 22:52:47 +01:00
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void ApplyToAllCacheEntries(void (*callback)(void*, size_t),
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bool thread_safe) override {
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2016-05-24 08:35:23 +02:00
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// only apply to _cache since key_only_cache doesn't hold value
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cache_->ApplyToAllCacheEntries(callback, thread_safe);
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}
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New Cache API for gathering statistics (#8225)
Summary:
Adds a new Cache::ApplyToAllEntries API that we expect to use
(in follow-up PRs) for efficiently gathering block cache statistics.
Notable features vs. old ApplyToAllCacheEntries:
* Includes key and deleter (in addition to value and charge). We could
have passed in a Handle but then more virtual function calls would be
needed to get the "fields" of each entry. We expect to use the 'deleter'
to identify the origin of entries, perhaps even more.
* Heavily tuned to minimize latency impact on operating cache. It
does this by iterating over small sections of each cache shard while
cycling through the shards.
* Supports tuning roughly how many entries to operate on for each
lock acquire and release, to control the impact on the latency of other
operations without excessive lock acquire & release. The right balance
can depend on the cost of the callback. Good default seems to be
around 256.
* There should be no need to disable thread safety. (I would expect
uncontended locks to be sufficiently fast.)
I have enhanced cache_bench to validate this approach:
* Reports a histogram of ns per operation, so we can look at the
ditribution of times, not just throughput (average).
* Can add a thread for simulated "gather stats" which calls
ApplyToAllEntries at a specified interval. We also generate a histogram
of time to run ApplyToAllEntries.
To make the iteration over some entries of each shard work as cleanly as
possible, even with resize between next set of entries, I have
re-arranged which hash bits are used for sharding and which for indexing
within a shard.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/8225
Test Plan:
A couple of unit tests are added, but primary validation is manual, as
the primary risk is to performance.
The primary validation is using cache_bench to ensure that neither
the minor hashing changes nor the simulated stats gathering
significantly impact QPS or latency distribution. Note that adding op
latency histogram seriously impacts the benchmark QPS, so for a
fair baseline, we need the cache_bench changes (except remove simulated
stat gathering to make it compile). In short, we don't see any
reproducible difference in ops/sec or op latency unless we are gathering
stats nearly continuously. Test uses 10GB block cache with
8KB values to be somewhat realistic in the number of items to iterate
over.
Baseline typical output:
```
Complete in 92.017 s; Rough parallel ops/sec = 869401
Thread ops/sec = 54662
Operation latency (ns):
Count: 80000000 Average: 11223.9494 StdDev: 29.61
Min: 0 Median: 7759.3973 Max: 9620500
Percentiles: P50: 7759.40 P75: 14190.73 P99: 46922.75 P99.9: 77509.84 P99.99: 217030.58
------------------------------------------------------
[ 0, 1 ] 68 0.000% 0.000%
( 2900, 4400 ] 89 0.000% 0.000%
( 4400, 6600 ] 33630240 42.038% 42.038% ########
( 6600, 9900 ] 18129842 22.662% 64.700% #####
( 9900, 14000 ] 7877533 9.847% 74.547% ##
( 14000, 22000 ] 15193238 18.992% 93.539% ####
( 22000, 33000 ] 3037061 3.796% 97.335% #
( 33000, 50000 ] 1626316 2.033% 99.368%
( 50000, 75000 ] 421532 0.527% 99.895%
( 75000, 110000 ] 56910 0.071% 99.966%
( 110000, 170000 ] 16134 0.020% 99.986%
( 170000, 250000 ] 5166 0.006% 99.993%
( 250000, 380000 ] 3017 0.004% 99.996%
( 380000, 570000 ] 1337 0.002% 99.998%
( 570000, 860000 ] 805 0.001% 99.999%
( 860000, 1200000 ] 319 0.000% 100.000%
( 1200000, 1900000 ] 231 0.000% 100.000%
( 1900000, 2900000 ] 100 0.000% 100.000%
( 2900000, 4300000 ] 39 0.000% 100.000%
( 4300000, 6500000 ] 16 0.000% 100.000%
( 6500000, 9800000 ] 7 0.000% 100.000%
```
New, gather_stats=false. Median thread ops/sec of 5 runs:
```
Complete in 92.030 s; Rough parallel ops/sec = 869285
Thread ops/sec = 54458
Operation latency (ns):
Count: 80000000 Average: 11298.1027 StdDev: 42.18
Min: 0 Median: 7722.0822 Max: 6398720
Percentiles: P50: 7722.08 P75: 14294.68 P99: 47522.95 P99.9: 85292.16 P99.99: 228077.78
------------------------------------------------------
[ 0, 1 ] 109 0.000% 0.000%
( 2900, 4400 ] 793 0.001% 0.001%
( 4400, 6600 ] 34054563 42.568% 42.569% #########
( 6600, 9900 ] 17482646 21.853% 64.423% ####
( 9900, 14000 ] 7908180 9.885% 74.308% ##
( 14000, 22000 ] 15032072 18.790% 93.098% ####
( 22000, 33000 ] 3237834 4.047% 97.145% #
( 33000, 50000 ] 1736882 2.171% 99.316%
( 50000, 75000 ] 446851 0.559% 99.875%
( 75000, 110000 ] 68251 0.085% 99.960%
( 110000, 170000 ] 18592 0.023% 99.983%
( 170000, 250000 ] 7200 0.009% 99.992%
( 250000, 380000 ] 3334 0.004% 99.997%
( 380000, 570000 ] 1393 0.002% 99.998%
( 570000, 860000 ] 700 0.001% 99.999%
( 860000, 1200000 ] 293 0.000% 100.000%
( 1200000, 1900000 ] 196 0.000% 100.000%
( 1900000, 2900000 ] 69 0.000% 100.000%
( 2900000, 4300000 ] 32 0.000% 100.000%
( 4300000, 6500000 ] 10 0.000% 100.000%
```
New, gather_stats=true, 1 second delay between scans. Scans take about
1 second here so it's spending about 50% time scanning. Still the effect on
ops/sec and latency seems to be in the noise. Median thread ops/sec of 5 runs:
```
Complete in 91.890 s; Rough parallel ops/sec = 870608
Thread ops/sec = 54551
Operation latency (ns):
Count: 80000000 Average: 11311.2629 StdDev: 45.28
Min: 0 Median: 7686.5458 Max: 10018340
Percentiles: P50: 7686.55 P75: 14481.95 P99: 47232.60 P99.9: 79230.18 P99.99: 232998.86
------------------------------------------------------
[ 0, 1 ] 71 0.000% 0.000%
( 2900, 4400 ] 291 0.000% 0.000%
( 4400, 6600 ] 34492060 43.115% 43.116% #########
( 6600, 9900 ] 16727328 20.909% 64.025% ####
( 9900, 14000 ] 7845828 9.807% 73.832% ##
( 14000, 22000 ] 15510654 19.388% 93.220% ####
( 22000, 33000 ] 3216533 4.021% 97.241% #
( 33000, 50000 ] 1680859 2.101% 99.342%
( 50000, 75000 ] 439059 0.549% 99.891%
( 75000, 110000 ] 60540 0.076% 99.967%
( 110000, 170000 ] 14649 0.018% 99.985%
( 170000, 250000 ] 5242 0.007% 99.991%
( 250000, 380000 ] 3260 0.004% 99.995%
( 380000, 570000 ] 1599 0.002% 99.997%
( 570000, 860000 ] 1043 0.001% 99.999%
( 860000, 1200000 ] 471 0.001% 99.999%
( 1200000, 1900000 ] 275 0.000% 100.000%
( 1900000, 2900000 ] 143 0.000% 100.000%
( 2900000, 4300000 ] 60 0.000% 100.000%
( 4300000, 6500000 ] 27 0.000% 100.000%
( 6500000, 9800000 ] 7 0.000% 100.000%
( 9800000, 14000000 ] 1 0.000% 100.000%
Gather stats latency (us):
Count: 46 Average: 980387.5870 StdDev: 60911.18
Min: 879155 Median: 1033777.7778 Max: 1261431
Percentiles: P50: 1033777.78 P75: 1120666.67 P99: 1261431.00 P99.9: 1261431.00 P99.99: 1261431.00
------------------------------------------------------
( 860000, 1200000 ] 45 97.826% 97.826% ####################
( 1200000, 1900000 ] 1 2.174% 100.000%
Most recent cache entry stats:
Number of entries: 1295133
Total charge: 9.88 GB
Average key size: 23.4982
Average charge: 8.00 KB
Unique deleters: 3
```
Reviewed By: mrambacher
Differential Revision: D28295742
Pulled By: pdillinger
fbshipit-source-id: bbc4a552f91ba0fe10e5cc025c42cef5a81f2b95
2021-05-12 01:16:11 +02:00
|
|
|
void ApplyToAllEntries(
|
|
|
|
const std::function<void(const Slice& key, void* value, size_t charge,
|
|
|
|
DeleterFn deleter)>& callback,
|
|
|
|
const ApplyToAllEntriesOptions& opts) override {
|
|
|
|
cache_->ApplyToAllEntries(callback, opts);
|
|
|
|
}
|
|
|
|
|
2019-02-14 22:52:47 +01:00
|
|
|
void EraseUnRefEntries() override {
|
2016-05-24 08:35:23 +02:00
|
|
|
cache_->EraseUnRefEntries();
|
|
|
|
key_only_cache_->EraseUnRefEntries();
|
|
|
|
}
|
|
|
|
|
2019-02-14 22:52:47 +01:00
|
|
|
size_t GetSimCapacity() const override {
|
2016-05-24 08:35:23 +02:00
|
|
|
return key_only_cache_->GetCapacity();
|
|
|
|
}
|
2019-02-14 22:52:47 +01:00
|
|
|
size_t GetSimUsage() const override { return key_only_cache_->GetUsage(); }
|
|
|
|
void SetSimCapacity(size_t capacity) override {
|
2016-05-24 08:35:23 +02:00
|
|
|
key_only_cache_->SetCapacity(capacity);
|
|
|
|
}
|
|
|
|
|
2019-02-14 22:52:47 +01:00
|
|
|
uint64_t get_miss_counter() const override {
|
2016-08-11 02:42:24 +02:00
|
|
|
return miss_times_.load(std::memory_order_relaxed);
|
2016-07-15 19:41:36 +02:00
|
|
|
}
|
|
|
|
|
2019-02-14 22:52:47 +01:00
|
|
|
uint64_t get_hit_counter() const override {
|
2016-07-15 19:41:36 +02:00
|
|
|
return hit_times_.load(std::memory_order_relaxed);
|
|
|
|
}
|
|
|
|
|
2019-02-14 22:52:47 +01:00
|
|
|
void reset_counter() override {
|
2016-08-11 02:42:24 +02:00
|
|
|
miss_times_.store(0, std::memory_order_relaxed);
|
2016-07-15 19:41:36 +02:00
|
|
|
hit_times_.store(0, std::memory_order_relaxed);
|
2016-08-11 02:42:24 +02:00
|
|
|
SetTickerCount(stats_, SIM_BLOCK_CACHE_HIT, 0);
|
|
|
|
SetTickerCount(stats_, SIM_BLOCK_CACHE_MISS, 0);
|
2016-05-24 08:35:23 +02:00
|
|
|
}
|
|
|
|
|
2019-02-14 22:52:47 +01:00
|
|
|
std::string ToString() const override {
|
2016-05-24 08:35:23 +02:00
|
|
|
std::string res;
|
2016-08-11 02:42:24 +02:00
|
|
|
res.append("SimCache MISSes: " + std::to_string(get_miss_counter()) + "\n");
|
2016-05-24 08:35:23 +02:00
|
|
|
res.append("SimCache HITs: " + std::to_string(get_hit_counter()) + "\n");
|
2016-12-15 04:20:42 +01:00
|
|
|
char buff[350];
|
2016-08-11 02:42:24 +02:00
|
|
|
auto lookups = get_miss_counter() + get_hit_counter();
|
2016-05-24 08:35:23 +02:00
|
|
|
snprintf(buff, sizeof(buff), "SimCache HITRATE: %.2f%%\n",
|
2016-08-11 02:42:24 +02:00
|
|
|
(lookups == 0 ? 0 : get_hit_counter() * 100.0f / lookups));
|
2016-05-24 08:35:23 +02:00
|
|
|
res.append(buff);
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
2019-02-14 22:52:47 +01:00
|
|
|
std::string GetPrintableOptions() const override {
|
2016-12-22 23:44:01 +01:00
|
|
|
std::string ret;
|
|
|
|
ret.reserve(20000);
|
|
|
|
ret.append(" cache_options:\n");
|
|
|
|
ret.append(cache_->GetPrintableOptions());
|
|
|
|
ret.append(" sim_cache_options:\n");
|
|
|
|
ret.append(key_only_cache_->GetPrintableOptions());
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2019-02-14 22:52:47 +01:00
|
|
|
Status StartActivityLogging(const std::string& activity_log_file, Env* env,
|
|
|
|
uint64_t max_logging_size = 0) override {
|
2017-07-28 21:18:09 +02:00
|
|
|
return cache_activity_logger_.StartLogging(activity_log_file, env,
|
|
|
|
max_logging_size);
|
|
|
|
}
|
|
|
|
|
2019-02-14 22:52:47 +01:00
|
|
|
void StopActivityLogging() override { cache_activity_logger_.StopLogging(); }
|
2017-07-28 21:18:09 +02:00
|
|
|
|
2019-02-14 22:52:47 +01:00
|
|
|
Status GetActivityLoggingStatus() override {
|
2017-07-28 21:18:09 +02:00
|
|
|
return cache_activity_logger_.bg_status();
|
|
|
|
}
|
|
|
|
|
2016-05-24 08:35:23 +02:00
|
|
|
private:
|
|
|
|
std::shared_ptr<Cache> cache_;
|
|
|
|
std::shared_ptr<Cache> key_only_cache_;
|
2016-08-11 02:42:24 +02:00
|
|
|
std::atomic<uint64_t> miss_times_;
|
2016-05-24 08:35:23 +02:00
|
|
|
std::atomic<uint64_t> hit_times_;
|
2016-08-11 02:42:24 +02:00
|
|
|
Statistics* stats_;
|
2017-07-28 21:18:09 +02:00
|
|
|
CacheActivityLogger cache_activity_logger_;
|
|
|
|
|
2016-08-11 02:42:24 +02:00
|
|
|
void inc_miss_counter() {
|
|
|
|
miss_times_.fetch_add(1, std::memory_order_relaxed);
|
2016-07-15 19:41:36 +02:00
|
|
|
}
|
|
|
|
void inc_hit_counter() { hit_times_.fetch_add(1, std::memory_order_relaxed); }
|
2016-05-24 08:35:23 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
} // end anonymous namespace
|
|
|
|
|
|
|
|
// For instrumentation purpose, use NewSimCache instead
|
|
|
|
std::shared_ptr<SimCache> NewSimCache(std::shared_ptr<Cache> cache,
|
2016-09-01 22:50:39 +02:00
|
|
|
size_t sim_capacity, int num_shard_bits) {
|
2019-09-17 00:14:51 +02:00
|
|
|
LRUCacheOptions co;
|
|
|
|
co.capacity = sim_capacity;
|
|
|
|
co.num_shard_bits = num_shard_bits;
|
|
|
|
co.metadata_charge_policy = kDontChargeCacheMetadata;
|
|
|
|
return NewSimCache(NewLRUCache(co), cache, num_shard_bits);
|
Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
2019-06-18 01:33:40 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
std::shared_ptr<SimCache> NewSimCache(std::shared_ptr<Cache> sim_cache,
|
|
|
|
std::shared_ptr<Cache> cache,
|
|
|
|
int num_shard_bits) {
|
2016-05-24 08:35:23 +02:00
|
|
|
if (num_shard_bits >= 20) {
|
|
|
|
return nullptr; // the cache cannot be sharded into too many fine pieces
|
|
|
|
}
|
Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
2019-06-18 01:33:40 +02:00
|
|
|
return std::make_shared<SimCacheImpl>(sim_cache, cache);
|
2016-05-24 08:35:23 +02:00
|
|
|
}
|
|
|
|
|
2020-02-20 21:07:53 +01:00
|
|
|
} // namespace ROCKSDB_NAMESPACE
|