2003-11-19 09:32:38 +01:00
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/*
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* $Id$
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*
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* Copyright <EFBFBD> 2003 Eric Anholt
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that
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* copyright notice and this permission notice appear in supporting
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* documentation, and that the name of Eric Anholt not be used in
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* advertising or publicity pertaining to distribution of the software without
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* specific, written prior permission. Eric Anholt makes no
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* representations about the suitability of this software for any purpose. It
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* is provided "as is" without express or implied warranty.
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*
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* ERIC ANHOLT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL ERIC ANHOLT BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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/* $Header$ */
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2003-12-30 09:23:56 +01:00
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/* Many of the Radeon register defines are the same for the r128 */
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2003-12-29 07:24:01 +01:00
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#define RADEON_REG_BUS_CNTL 0x0030
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# define RADEON_BUS_MASTER_DIS (1 << 6)
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2003-12-30 09:23:56 +01:00
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2003-12-29 07:24:01 +01:00
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#define RADEON_GEN_INT_CNTL 0x0040
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#define RADEON_REG_AGP_BASE 0x0170
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2003-12-30 09:23:56 +01:00
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2003-12-29 07:24:01 +01:00
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#define RADEON_REG_AGP_CNTL 0x0174
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# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)
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# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)
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# define RADEON_AGP_APER_SIZE_64MB (0x30 << 0)
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# define RADEON_AGP_APER_SIZE_32MB (0x38 << 0)
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# define RADEON_AGP_APER_SIZE_16MB (0x3c << 0)
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# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)
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# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)
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# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)
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2003-12-30 09:23:56 +01:00
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2003-11-19 09:32:38 +01:00
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#define RADEON_REG_RBBM_STATUS 0x0e40
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# define RADEON_RBBM_FIFOCNT_MASK 0x007f
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# define RADEON_RBBM_ACTIVE (1 << 31)
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2003-12-30 09:23:56 +01:00
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2003-12-29 07:24:01 +01:00
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#define RADEON_REG_CP_CSQ_CNTL 0x0740
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# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
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2003-11-20 08:49:46 +01:00
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#define RADEON_REG_SRC_PITCH_OFFSET 0x1428
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#define RADEON_REG_DST_PITCH_OFFSET 0x142c
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2003-11-19 09:32:38 +01:00
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#define RADEON_REG_SRC_Y_X 0x1434
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#define RADEON_REG_DST_Y_X 0x1438
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#define RADEON_REG_DST_HEIGHT_WIDTH 0x143c
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2003-11-19 09:32:38 +01:00
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#define RADEON_REG_DP_GUI_MASTER_CNTL 0x146c
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2003-11-20 08:49:46 +01:00
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# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
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# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
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2003-11-19 09:32:38 +01:00
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# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
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# define RADEON_GMC_BRUSH_NONE (15 << 4)
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# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
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# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
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# define RADEON_GMC_3D_FCN_EN (1 << 27)
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2003-11-19 09:32:38 +01:00
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# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
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# define RADEON_GMC_AUX_CLIP_DIS (1 << 29)
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2003-12-29 07:24:01 +01:00
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#define RADEON_REG_DP_BRUSH_FRGD_CLR 0x147c
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#define RADEON_REG_DST_WIDTH_HEIGHT 0x1598
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#define RADEON_REG_CLR_CMP_CNTL 0x15c0
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#define RADEON_REG_AUX_SC_CNTL 0x1660
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2003-11-19 09:32:38 +01:00
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#define RADEON_REG_DP_CNTL 0x16c0
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# define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0)
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# define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1)
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2003-12-29 07:24:01 +01:00
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#define RADEON_REG_DP_MIX 0x16c8
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#define RADEON_REG_DP_WRITE_MASK 0x16cc
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#define RADEON_REG_DEFAULT_OFFSET 0x16e0
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#define RADEON_REG_DEFAULT_PITCH 0x16e4
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2003-11-19 09:32:38 +01:00
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#define RADEON_REG_DEFAULT_SC_BOTTOM_RIGHT 0x16e8
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# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
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# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
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2003-12-30 09:23:56 +01:00
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2003-11-19 09:32:38 +01:00
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#define RADEON_REG_SC_TOP_LEFT 0x16ec
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#define RADEON_REG_SC_BOTTOM_RIGHT 0x16f0
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2003-12-30 09:23:56 +01:00
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#define RADEON_REG_WAIT_UNTIL 0x1720
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# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
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# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
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# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
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# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
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#define RADEON_RB3D_BLENDCNTL 0x1c20
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# define RADEON_COMB_FCN_MASK (3 << 12)
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# define RADEON_COMB_FCN_ADD_CLAMP (0 << 12)
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# define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12)
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# define RADEON_COMB_FCN_SUB_CLAMP (2 << 12)
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# define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12)
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# define RADEON_SRC_BLEND_GL_ZERO (32 << 16)
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# define RADEON_SRC_BLEND_GL_ONE (33 << 16)
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# define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16)
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# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16)
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# define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16)
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# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16)
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# define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16)
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# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16)
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# define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16)
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# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16)
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# define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16)
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# define RADEON_SRC_BLEND_MASK (63 << 16)
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# define RADEON_DST_BLEND_GL_ZERO (32 << 24)
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# define RADEON_DST_BLEND_GL_ONE (33 << 24)
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# define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24)
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# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24)
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# define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24)
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# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24)
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# define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24)
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# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24)
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# define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24)
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# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24)
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# define RADEON_DST_BLEND_MASK (63 << 24)
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#define RADEON_REG_PP_CNTL 0x1c38
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# define RADEON_STIPPLE_ENABLE (1 << 0)
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# define RADEON_SCISSOR_ENABLE (1 << 1)
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# define RADEON_PATTERN_ENABLE (1 << 2)
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# define RADEON_SHADOW_ENABLE (1 << 3)
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# define RADEON_TEX_ENABLE_MASK (0xf << 4)
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# define RADEON_TEX_0_ENABLE (1 << 4)
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# define RADEON_TEX_1_ENABLE (1 << 5)
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# define RADEON_TEX_2_ENABLE (1 << 6)
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# define RADEON_TEX_3_ENABLE (1 << 7)
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# define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12)
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# define RADEON_TEX_BLEND_0_ENABLE (1 << 12)
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# define RADEON_TEX_BLEND_1_ENABLE (1 << 13)
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# define RADEON_TEX_BLEND_2_ENABLE (1 << 14)
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# define RADEON_TEX_BLEND_3_ENABLE (1 << 15)
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# define RADEON_PLANAR_YUV_ENABLE (1 << 20)
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# define RADEON_SPECULAR_ENABLE (1 << 21)
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# define RADEON_FOG_ENABLE (1 << 22)
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# define RADEON_ALPHA_TEST_ENABLE (1 << 23)
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# define RADEON_ANTI_ALIAS_NONE (0 << 24)
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# define RADEON_ANTI_ALIAS_LINE (1 << 24)
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# define RADEON_ANTI_ALIAS_POLY (2 << 24)
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# define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24)
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# define RADEON_BUMP_MAP_ENABLE (1 << 26)
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# define RADEON_BUMPED_MAP_T0 (0 << 27)
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# define RADEON_BUMPED_MAP_T1 (1 << 27)
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# define RADEON_BUMPED_MAP_T2 (2 << 27)
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# define RADEON_TEX_3D_ENABLE_0 (1 << 29)
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# define RADEON_TEX_3D_ENABLE_1 (1 << 30)
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# define RADEON_MC_ENABLE (1 << 31)
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#define RADEON_REG_RB3D_CNTL 0x1c3c
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# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
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# define RADEON_PLANE_MASK_ENABLE (1 << 1)
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# define RADEON_DITHER_ENABLE (1 << 2)
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# define RADEON_ROUND_ENABLE (1 << 3)
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# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
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# define RADEON_DITHER_INIT (1 << 5)
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# define RADEON_ROP_ENABLE (1 << 6)
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# define RADEON_STENCIL_ENABLE (1 << 7)
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# define RADEON_Z_ENABLE (1 << 8)
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# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9)
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# define RADEON_COLOR_FORMAT_ARGB1555 (3 << 10)
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# define RADEON_COLOR_FORMAT_RGB565 (4 << 10)
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# define RADEON_COLOR_FORMAT_ARGB8888 (6 << 10)
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# define RADEON_COLOR_FORMAT_RGB332 (7 << 10)
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# define RADEON_COLOR_FORMAT_Y8 (8 << 10)
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# define RADEON_COLOR_FORMAT_RGB8 (9 << 10)
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# define RADEON_COLOR_FORMAT_YUV422_VYUY (11 << 10)
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# define RADEON_COLOR_FORMAT_YUV422_YVYU (12 << 10)
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# define RADEON_COLOR_FORMAT_aYUV444 (14 << 10)
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# define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10)
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# define RADEON_CLRCMP_FLIP_ENABLE (1 << 14)
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#define RADEON_REG_RB3D_COLOROFFSET 0x1c40
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# define RADEON_COLOROFFSET_MASK 0xfffffff0
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#define RADEON_REG_RE_WIDTH_HEIGHT 0x1c44
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#define RADEON_REG_RB3D_COLORPITCH 0x1c48
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# define RADEON_COLORPITCH_MASK 0x000001ff8
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# define RADEON_COLOR_TILE_ENABLE (1 << 16)
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# define RADEON_COLOR_MICROTILE_ENABLE (1 << 17)
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# define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18)
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# define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18)
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# define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18)
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#define RADEON_REG_SE_CNTL 0x1c4c
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# define RADEON_FFACE_CULL_CW (0 << 0)
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# define RADEON_FFACE_CULL_CCW (1 << 0)
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# define RADEON_FFACE_CULL_DIR_MASK (1 << 0)
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# define RADEON_BFACE_CULL (0 << 1)
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# define RADEON_BFACE_SOLID (3 << 1)
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# define RADEON_FFACE_CULL (0 << 3)
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# define RADEON_FFACE_SOLID (3 << 3)
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# define RADEON_FFACE_CULL_MASK (3 << 3)
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# define RADEON_BADVTX_CULL_DISABLE (1 << 5)
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# define RADEON_FLAT_SHADE_VTX_0 (0 << 6)
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# define RADEON_FLAT_SHADE_VTX_1 (1 << 6)
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# define RADEON_FLAT_SHADE_VTX_2 (2 << 6)
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# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
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# define RADEON_DIFFUSE_SHADE_SOLID (0 << 8)
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# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
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# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
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# define RADEON_DIFFUSE_SHADE_MASK (3 << 8)
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# define RADEON_ALPHA_SHADE_SOLID (0 << 10)
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# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
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# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
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# define RADEON_ALPHA_SHADE_MASK (3 << 10)
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# define RADEON_SPECULAR_SHADE_SOLID (0 << 12)
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# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
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# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
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# define RADEON_SPECULAR_SHADE_MASK (3 << 12)
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# define RADEON_FOG_SHADE_SOLID (0 << 14)
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# define RADEON_FOG_SHADE_FLAT (1 << 14)
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# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
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# define RADEON_FOG_SHADE_MASK (3 << 14)
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# define RADEON_ZBIAS_ENABLE_POINT (1 << 16)
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# define RADEON_ZBIAS_ENABLE_LINE (1 << 17)
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# define RADEON_ZBIAS_ENABLE_TRI (1 << 18)
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# define RADEON_WIDELINE_ENABLE (1 << 20)
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# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
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# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
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# define RADEON_VTX_PIX_CENTER_D3D (0 << 27)
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# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
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|
# define RADEON_ROUND_MODE_TRUNC (0 << 28)
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# define RADEON_ROUND_MODE_ROUND (1 << 28)
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# define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28)
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|
|
# define RADEON_ROUND_MODE_ROUND_ODD (3 << 28)
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|
|
# define RADEON_ROUND_PREC_16TH_PIX (0 << 30)
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|
|
# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
|
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|
|
# define RADEON_ROUND_PREC_4TH_PIX (2 << 30)
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# define RADEON_ROUND_PREC_HALF_PIX (3 << 30)
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#define RADEON_REG_SE_COORD_FMT 0x1c50
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|
# define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0)
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|
|
# define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1)
|
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|
|
# define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8)
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|
|
# define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9)
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# define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10)
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|
|
# define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11)
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|
|
# define RADEON_VTX_W0_NORMALIZE (1 << 12)
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|
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# define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16)
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# define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17)
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|
|
# define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19)
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# define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21)
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# define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23)
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# define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26)
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# define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26)
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#define RADEON_REG_PP_TXFILTER_0 0x1c54
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#define RADEON_REG_PP_TXFILTER_1 0x1c6c
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#define RADEON_REG_PP_TXFILTER_2 0x1c84
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# define RADEON_MAG_FILTER_NEAREST (0 << 0)
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# define RADEON_MAG_FILTER_LINEAR (1 << 0)
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|
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# define RADEON_MAG_FILTER_MASK (1 << 0)
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# define RADEON_MIN_FILTER_NEAREST (0 << 1)
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# define RADEON_MIN_FILTER_LINEAR (1 << 1)
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|
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# define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)
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# define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)
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|
|
# define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)
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|
|
# define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)
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|
|
# define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1)
|
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|
|
# define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1)
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|
|
# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)
|
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|
|
# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)
|
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|
|
# define RADEON_MIN_FILTER_MASK (15 << 1)
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|
|
# define RADEON_MAX_ANISO_1_TO_1 (0 << 5)
|
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|
|
# define RADEON_MAX_ANISO_2_TO_1 (1 << 5)
|
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|
|
# define RADEON_MAX_ANISO_4_TO_1 (2 << 5)
|
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|
|
# define RADEON_MAX_ANISO_8_TO_1 (3 << 5)
|
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|
|
# define RADEON_MAX_ANISO_16_TO_1 (4 << 5)
|
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|
|
# define RADEON_MAX_ANISO_MASK (7 << 5)
|
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|
|
# define RADEON_LOD_BIAS_MASK (0xff << 8)
|
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|
|
# define RADEON_LOD_BIAS_SHIFT 8
|
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|
|
# define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16)
|
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|
|
# define RADEON_MAX_MIP_LEVEL_SHIFT 16
|
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|
|
# define RADEON_YUV_TO_RGB (1 << 20)
|
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|
|
# define RADEON_YUV_TEMPERATURE_COOL (0 << 21)
|
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|
|
# define RADEON_YUV_TEMPERATURE_HOT (1 << 21)
|
|
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|
|
# define RADEON_YUV_TEMPERATURE_MASK (1 << 21)
|
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|
|
# define RADEON_WRAPEN_S (1 << 22)
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|
|
# define RADEON_CLAMP_S_WRAP (0 << 23)
|
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|
|
# define RADEON_CLAMP_S_MIRROR (1 << 23)
|
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|
|
# define RADEON_CLAMP_S_CLAMP_LAST (2 << 23)
|
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|
|
# define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)
|
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|
|
# define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23)
|
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|
|
# define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)
|
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|
|
# define RADEON_CLAMP_S_CLAMP_GL (6 << 23)
|
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|
|
# define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)
|
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|
|
# define RADEON_CLAMP_S_MASK (7 << 23)
|
|
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|
|
# define RADEON_WRAPEN_T (1 << 26)
|
|
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|
|
# define RADEON_CLAMP_T_WRAP (0 << 27)
|
|
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|
|
# define RADEON_CLAMP_T_MIRROR (1 << 27)
|
|
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|
|
# define RADEON_CLAMP_T_CLAMP_LAST (2 << 27)
|
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|
|
# define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)
|
|
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|
|
# define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27)
|
|
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|
|
# define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)
|
|
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|
|
# define RADEON_CLAMP_T_CLAMP_GL (6 << 27)
|
|
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|
|
# define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)
|
|
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|
|
# define RADEON_CLAMP_T_MASK (7 << 27)
|
|
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|
|
# define RADEON_BORDER_MODE_OGL (0 << 31)
|
|
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|
|
# define RADEON_BORDER_MODE_D3D (1 << 31)
|
|
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|
|
#define RADEON_REG_PP_TXFORMAT_0 0x1c58
|
|
|
|
|
#define RADEON_REG_PP_TXFORMAT_1 0x1c70
|
|
|
|
|
#define RADEON_REG_PP_TXFORMAT_2 0x1c88
|
|
|
|
|
# define RADEON_TXFORMAT_I8 (0 << 0)
|
|
|
|
|
# define RADEON_TXFORMAT_AI88 (1 << 0)
|
|
|
|
|
# define RADEON_TXFORMAT_RGB332 (2 << 0)
|
|
|
|
|
# define RADEON_TXFORMAT_ARGB1555 (3 << 0)
|
|
|
|
|
# define RADEON_TXFORMAT_RGB565 (4 << 0)
|
|
|
|
|
# define RADEON_TXFORMAT_ARGB4444 (5 << 0)
|
|
|
|
|
# define RADEON_TXFORMAT_ARGB8888 (6 << 0)
|
|
|
|
|
# define RADEON_TXFORMAT_RGBA8888 (7 << 0)
|
|
|
|
|
# define RADEON_TXFORMAT_Y8 (8 << 0)
|
|
|
|
|
# define RADEON_TXFORMAT_VYUY422 (10 << 0)
|
|
|
|
|
# define RADEON_TXFORMAT_YVYU422 (11 << 0)
|
|
|
|
|
# define RADEON_TXFORMAT_DXT1 (12 << 0)
|
|
|
|
|
# define RADEON_TXFORMAT_DXT23 (14 << 0)
|
|
|
|
|
# define RADEON_TXFORMAT_DXT45 (15 << 0)
|
|
|
|
|
# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0)
|
|
|
|
|
# define RADEON_TXFORMAT_FORMAT_SHIFT 0
|
|
|
|
|
# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5)
|
|
|
|
|
# define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6)
|
|
|
|
|
# define RADEON_TXFORMAT_NON_POWER2 (1 << 7)
|
|
|
|
|
# define RADEON_TXFORMAT_WIDTH_MASK (15 << 8)
|
|
|
|
|
# define RADEON_TXFORMAT_WIDTH_SHIFT 8
|
|
|
|
|
# define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12)
|
|
|
|
|
# define RADEON_TXFORMAT_HEIGHT_SHIFT 12
|
|
|
|
|
# define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16)
|
|
|
|
|
# define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16
|
|
|
|
|
# define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20)
|
|
|
|
|
# define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20
|
|
|
|
|
# define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)
|
|
|
|
|
# define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24)
|
|
|
|
|
# define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)
|
|
|
|
|
# define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)
|
|
|
|
|
# define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26)
|
|
|
|
|
# define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26)
|
|
|
|
|
# define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26)
|
|
|
|
|
# define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26)
|
|
|
|
|
# define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)
|
|
|
|
|
# define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)
|
|
|
|
|
# define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)
|
|
|
|
|
# define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31)
|
|
|
|
|
|
|
|
|
|
#define RADEON_REG_PP_TXOFFSET_0 0x1c5c
|
|
|
|
|
#define RADEON_REG_PP_TXOFFSET_1 0x1c74
|
|
|
|
|
#define RADEON_REG_PP_TXOFFSET_2 0x1c8c
|
|
|
|
|
# define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0)
|
|
|
|
|
# define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0)
|
|
|
|
|
# define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0)
|
|
|
|
|
# define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
|
|
|
|
|
# define RADEON_TXO_MACRO_LINEAR (0 << 2)
|
|
|
|
|
# define RADEON_TXO_MACRO_TILE (1 << 2)
|
|
|
|
|
# define RADEON_TXO_MICRO_LINEAR (0 << 3)
|
|
|
|
|
# define RADEON_TXO_MICRO_TILE_X2 (1 << 3)
|
|
|
|
|
# define RADEON_TXO_MICRO_TILE_OPT (2 << 3)
|
|
|
|
|
# define RADEON_TXO_OFFSET_MASK 0xffffffe0
|
|
|
|
|
# define RADEON_TXO_OFFSET_SHIFT 5
|
|
|
|
|
|
|
|
|
|
#define RADEON_REG_PP_TXCBLEND_0 0x1c60
|
|
|
|
|
#define RADEON_REG_PP_TXCBLEND_1 0x1c78
|
|
|
|
|
#define RADEON_REG_PP_TXCBLEND_2 0x1c90
|
|
|
|
|
# define RADEON_COLOR_ARG_A_SHIFT 0
|
|
|
|
|
# define RADEON_COLOR_ARG_A_MASK (0x1f << 0)
|
|
|
|
|
# define RADEON_COLOR_ARG_A_ZERO (0 << 0)
|
|
|
|
|
# define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0)
|
|
|
|
|
# define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0)
|
|
|
|
|
# define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0)
|
|
|
|
|
# define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0)
|
|
|
|
|
# define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0)
|
|
|
|
|
# define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0)
|
|
|
|
|
# define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0)
|
|
|
|
|
# define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0)
|
|
|
|
|
# define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0)
|
|
|
|
|
# define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0)
|
|
|
|
|
# define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0)
|
|
|
|
|
# define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0)
|
|
|
|
|
# define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0)
|
|
|
|
|
# define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0)
|
|
|
|
|
# define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0)
|
|
|
|
|
# define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0)
|
|
|
|
|
# define RADEON_COLOR_ARG_B_SHIFT 5
|
|
|
|
|
# define RADEON_COLOR_ARG_B_MASK (0x1f << 5)
|
|
|
|
|
# define RADEON_COLOR_ARG_B_ZERO (0 << 5)
|
|
|
|
|
# define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5)
|
|
|
|
|
# define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5)
|
|
|
|
|
# define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5)
|
|
|
|
|
# define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5)
|
|
|
|
|
# define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5)
|
|
|
|
|
# define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5)
|
|
|
|
|
# define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5)
|
|
|
|
|
# define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5)
|
|
|
|
|
# define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5)
|
|
|
|
|
# define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5)
|
|
|
|
|
# define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5)
|
|
|
|
|
# define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5)
|
|
|
|
|
# define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5)
|
|
|
|
|
# define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5)
|
|
|
|
|
# define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5)
|
|
|
|
|
# define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5)
|
|
|
|
|
# define RADEON_COLOR_ARG_C_SHIFT 10
|
|
|
|
|
# define RADEON_COLOR_ARG_C_MASK (0x1f << 10)
|
|
|
|
|
# define RADEON_COLOR_ARG_C_ZERO (0 << 10)
|
|
|
|
|
# define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10)
|
|
|
|
|
# define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10)
|
|
|
|
|
# define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10)
|
|
|
|
|
# define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10)
|
|
|
|
|
# define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10)
|
|
|
|
|
# define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10)
|
|
|
|
|
# define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10)
|
|
|
|
|
# define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10)
|
|
|
|
|
# define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10)
|
|
|
|
|
# define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10)
|
|
|
|
|
# define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10)
|
|
|
|
|
# define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10)
|
|
|
|
|
# define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10)
|
|
|
|
|
# define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10)
|
|
|
|
|
# define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10)
|
|
|
|
|
# define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10)
|
|
|
|
|
# define RADEON_COMP_ARG_A (1 << 15)
|
|
|
|
|
# define RADEON_COMP_ARG_A_SHIFT 15
|
|
|
|
|
# define RADEON_COMP_ARG_B (1 << 16)
|
|
|
|
|
# define RADEON_COMP_ARG_B_SHIFT 16
|
|
|
|
|
# define RADEON_COMP_ARG_C (1 << 17)
|
|
|
|
|
# define RADEON_COMP_ARG_C_SHIFT 17
|
|
|
|
|
# define RADEON_BLEND_CTL_MASK (7 << 18)
|
|
|
|
|
# define RADEON_BLEND_CTL_ADD (0 << 18)
|
|
|
|
|
# define RADEON_BLEND_CTL_SUBTRACT (1 << 18)
|
|
|
|
|
# define RADEON_BLEND_CTL_ADDSIGNED (2 << 18)
|
|
|
|
|
# define RADEON_BLEND_CTL_BLEND (3 << 18)
|
|
|
|
|
# define RADEON_BLEND_CTL_DOT3 (4 << 18)
|
|
|
|
|
# define RADEON_SCALE_SHIFT 21
|
|
|
|
|
# define RADEON_SCALE_MASK (3 << 21)
|
|
|
|
|
# define RADEON_SCALE_1X (0 << 21)
|
|
|
|
|
# define RADEON_SCALE_2X (1 << 21)
|
|
|
|
|
# define RADEON_SCALE_4X (2 << 21)
|
|
|
|
|
# define RADEON_CLAMP_TX (1 << 23)
|
|
|
|
|
# define RADEON_T0_EQ_TCUR (1 << 24)
|
|
|
|
|
# define RADEON_T1_EQ_TCUR (1 << 25)
|
|
|
|
|
# define RADEON_T2_EQ_TCUR (1 << 26)
|
|
|
|
|
# define RADEON_T3_EQ_TCUR (1 << 27)
|
|
|
|
|
# define RADEON_COLOR_ARG_MASK 0x1f
|
|
|
|
|
# define RADEON_COMP_ARG_SHIFT 15
|
|
|
|
|
|
|
|
|
|
#define RADEON_REG_PP_TXABLEND_0 0x1c64
|
|
|
|
|
#define RADEON_REG_PP_TXABLEND_1 0x1c7c
|
|
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#define RADEON_REG_PP_TXABLEND_2 0x1c94
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# define RADEON_ALPHA_ARG_A_SHIFT 0
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# define RADEON_ALPHA_ARG_A_MASK (0xf << 0)
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# define RADEON_ALPHA_ARG_A_ZERO (0 << 0)
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# define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0)
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# define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0)
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# define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0)
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# define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0)
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# define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0)
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# define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0)
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# define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0)
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# define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0)
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# define RADEON_ALPHA_ARG_B_SHIFT 4
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# define RADEON_ALPHA_ARG_B_MASK (0xf << 4)
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# define RADEON_ALPHA_ARG_B_ZERO (0 << 4)
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# define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4)
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# define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4)
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# define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4)
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# define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4)
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# define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4)
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# define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4)
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# define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4)
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# define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4)
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# define RADEON_ALPHA_ARG_C_SHIFT 8
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# define RADEON_ALPHA_ARG_C_MASK (0xf << 8)
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# define RADEON_ALPHA_ARG_C_ZERO (0 << 8)
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# define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8)
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# define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8)
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# define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8)
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# define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8)
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# define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8)
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# define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8)
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# define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8)
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# define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8)
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# define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9)
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# define RADEON_ALPHA_ARG_MASK 0xf
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#define RADEON_REG_PP_TFACTOR_0 0x1c68
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#define RADEON_REG_PP_TFACTOR_1 0x1c80
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#define RADEON_REG_PP_TFACTOR_2 0x1c98
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#define RADEON_REG_PP_TEX_SIZE_0 0x1d04 /* NPOT */
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|
#define RADEON_REG_PP_TEX_SIZE_1 0x1d0c
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#define RADEON_REG_PP_TEX_SIZE_2 0x1d14
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# define RADEON_TEX_USIZE_MASK (0x7ff << 0)
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# define RADEON_TEX_USIZE_SHIFT 0
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|
# define RADEON_TEX_VSIZE_MASK (0x7ff << 16)
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|
|
# define RADEON_TEX_VSIZE_SHIFT 16
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|
|
# define RADEON_SIGNED_RGB_MASK (1 << 30)
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|
|
# define RADEON_SIGNED_RGB_SHIFT 30
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|
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# define RADEON_SIGNED_ALPHA_MASK (1 << 31)
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|
# define RADEON_SIGNED_ALPHA_SHIFT 31
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#define RADEON_REG_PP_TEX_PITCH_0 0x1d08 /* NPOT */
|
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#define RADEON_REG_PP_TEX_PITCH_1 0x1d10 /* NPOT */
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#define RADEON_REG_PP_TEX_PITCH_2 0x1d18 /* NPOT */
|
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|
|
/* note: bits 13-5: 32 byte aligned stride of texture map */
|
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|
#define RADEON_REG_RB3D_PLANEMASK 0x1d84
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#define RADEON_REG_SE_CNTL_STATUS 0x2140
|
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|
|
# define RADEON_VC_NO_SWAP (0 << 0)
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|
|
# define RADEON_VC_16BIT_SWAP (1 << 0)
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|
|
# define RADEON_VC_32BIT_SWAP (2 << 0)
|
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|
|
# define RADEON_VC_HALF_DWORD_SWAP (3 << 0)
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|
|
# define RADEON_TCL_BYPASS (1 << 8)
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#define RADEON_REG_RE_TOP_LEFT 0x26c0
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|
|
2003-11-19 09:32:38 +01:00
|
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|
#define RADEON_REG_RB2D_DSTCACHE_CTLSTAT 0x342c
|
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|
|
# define RADEON_RB2D_DC_FLUSH (3 << 0)
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|
|
# define RADEON_RB2D_DC_FREE (3 << 2)
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|
|
# define RADEON_RB2D_DC_FLUSH_ALL 0xf
|
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|
|
# define RADEON_RB2D_DC_BUSY (1 << 31)
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|
|
2003-12-29 07:24:01 +01:00
|
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#define RADEON_CP_PACKET0 0x00000000
|
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|
|
#define RADEON_CP_PACKET1 0x40000000
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|
#define RADEON_CP_PACKET2 0x80000000
|
2003-12-30 09:23:56 +01:00
|
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|
|
#define RADEON_CP_PACKET3_NOP 0xC0001000
|
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|
|
#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900
|
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|
|
#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00
|
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|
|
#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00
|
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|
|
#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300
|
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|
|
#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400
|
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|
|
#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600
|
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|
|
#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800
|
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|
|
#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900
|
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|
|
#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00
|
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|
|
#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00
|
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|
|
#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00
|
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|
|
#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100
|
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|
|
#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200
|
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|
|
#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300
|
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|
|
#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400
|
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|
|
|
#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500
|
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|
|
#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800
|
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|
|
#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00
|
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|
|
#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00
|
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|
|
#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00
|
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|
|
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|
|
#define RADEON_CP_VC_FRMT_XY 0x00000000
|
|
|
|
|
#define RADEON_CP_VC_FRMT_W0 0x00000001
|
|
|
|
|
#define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002
|
|
|
|
|
#define RADEON_CP_VC_FRMT_FPALPHA 0x00000004
|
|
|
|
|
#define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008
|
|
|
|
|
#define RADEON_CP_VC_FRMT_FPSPEC 0x00000010
|
|
|
|
|
#define RADEON_CP_VC_FRMT_FPFOG 0x00000020
|
|
|
|
|
#define RADEON_CP_VC_FRMT_PKSPEC 0x00000040
|
|
|
|
|
#define RADEON_CP_VC_FRMT_ST0 0x00000080
|
|
|
|
|
#define RADEON_CP_VC_FRMT_ST1 0x00000100
|
|
|
|
|
#define RADEON_CP_VC_FRMT_Q1 0x00000200
|
|
|
|
|
#define RADEON_CP_VC_FRMT_ST2 0x00000400
|
|
|
|
|
#define RADEON_CP_VC_FRMT_Q2 0x00000800
|
|
|
|
|
#define RADEON_CP_VC_FRMT_ST3 0x00001000
|
|
|
|
|
#define RADEON_CP_VC_FRMT_Q3 0x00002000
|
|
|
|
|
#define RADEON_CP_VC_FRMT_Q0 0x00004000
|
|
|
|
|
#define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000
|
|
|
|
|
#define RADEON_CP_VC_FRMT_N0 0x00040000
|
|
|
|
|
#define RADEON_CP_VC_FRMT_XY1 0x08000000
|
|
|
|
|
#define RADEON_CP_VC_FRMT_Z1 0x10000000
|
|
|
|
|
#define RADEON_CP_VC_FRMT_W1 0x20000000
|
|
|
|
|
#define RADEON_CP_VC_FRMT_N1 0x40000000
|
|
|
|
|
#define RADEON_CP_VC_FRMT_Z 0x80000000
|
|
|
|
|
|
|
|
|
|
#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000
|
|
|
|
|
#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001
|
|
|
|
|
#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002
|
|
|
|
|
#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003
|
|
|
|
|
#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
|
|
|
|
|
#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
|
|
|
|
|
#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
|
|
|
|
|
#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007
|
|
|
|
|
#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008
|
|
|
|
|
#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009
|
|
|
|
|
#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a
|
|
|
|
|
#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010
|
|
|
|
|
#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020
|
|
|
|
|
#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030
|
|
|
|
|
#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000
|
|
|
|
|
#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040
|
|
|
|
|
#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080
|
|
|
|
|
#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000
|
|
|
|
|
#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100
|
|
|
|
|
#define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000
|
|
|
|
|
#define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200
|
|
|
|
|
#define RADEON_CP_VC_CNTL_NUM_SHIFT 16
|
2003-12-29 07:24:01 +01:00
|
|
|
|
|
2003-11-19 09:32:38 +01:00
|
|
|
|
#define R128_REG_PC_NGUI_CTLSTAT 0x0184
|
|
|
|
|
# define R128_PC_BUSY (1 << 31)
|
2003-12-29 07:24:01 +01:00
|
|
|
|
#define R128_REG_PCI_GART_PAGE 0x017c
|
|
|
|
|
#define R128_REG_PC_NGUI_CTLSTAT 0x0184
|
|
|
|
|
#define R128_REG_BM_CHUNK_0_VAL 0x0a18
|
|
|
|
|
# define R128_BM_PTR_FORCE_TO_PCI (1 << 21)
|
|
|
|
|
# define R128_BM_PM4_RD_FORCE_TO_PCI (1 << 22)
|
|
|
|
|
# define R128_BM_GLOBAL_FORCE_TO_PCI (1 << 23)
|
2003-11-19 09:32:38 +01:00
|
|
|
|
#define R128_REG_GUI_STAT 0x1740
|
|
|
|
|
# define R128_GUI_ACTIVE (1 << 31)
|
2003-12-29 07:24:01 +01:00
|
|
|
|
|
|
|
|
|
#define R128_REG_TEX_CNTL 0x1800
|
|
|
|
|
#define R128_REG_SCALE_SRC_HEIGHT_WIDTH 0x1994
|
|
|
|
|
#define R128_REG_SCALE_OFFSET_0 0x1998
|
|
|
|
|
#define R128_REG_SCALE_PITCH 0x199c
|
|
|
|
|
#define R128_REG_SCALE_X_INC 0x19a0
|
|
|
|
|
#define R128_REG_SCALE_Y_INC 0x19a4
|
|
|
|
|
#define R128_REG_SCALE_HACC 0x19a8
|
|
|
|
|
#define R128_REG_SCALE_VACC 0x19ac
|
|
|
|
|
#define R128_REG_SCALE_DST_X_Y 0x19b0
|
|
|
|
|
#define R128_REG_SCALE_DST_HEIGHT_WIDTH 0x19b4
|
|
|
|
|
|
|
|
|
|
#define R128_REG_SCALE_3D_CNTL 0x1a00
|
|
|
|
|
# define R128_SCALE_DITHER_ERR_DIFF (0 << 1)
|
|
|
|
|
# define R128_SCALE_DITHER_TABLE (1 << 1)
|
|
|
|
|
# define R128_TEX_CACHE_SIZE_FULL (0 << 2)
|
|
|
|
|
# define R128_TEX_CACHE_SIZE_HALF (1 << 2)
|
|
|
|
|
# define R128_DITHER_INIT_CURR (0 << 3)
|
|
|
|
|
# define R128_DITHER_INIT_RESET (1 << 3)
|
|
|
|
|
# define R128_ROUND_24BIT (1 << 4)
|
|
|
|
|
# define R128_TEX_CACHE_DISABLE (1 << 5)
|
|
|
|
|
# define R128_SCALE_3D_NOOP (0 << 6)
|
|
|
|
|
# define R128_SCALE_3D_SCALE (1 << 6)
|
|
|
|
|
# define R128_SCALE_3D_TEXMAP_SHADE (2 << 6)
|
|
|
|
|
# define R128_SCALE_PIX_BLEND (0 << 8)
|
|
|
|
|
# define R128_SCALE_PIX_REPLICATE (1 << 8)
|
|
|
|
|
# define R128_TEX_CACHE_SPLIT (1 << 9)
|
|
|
|
|
# define R128_APPLE_YUV_MODE (1 << 10)
|
|
|
|
|
# define R128_TEX_CACHE_PALLETE_MODE (1 << 11)
|
|
|
|
|
# define R128_ALPHA_COMB_ADD_CLAMP (0 << 12)
|
|
|
|
|
# define R128_ALPHA_COMB_ADD_NCLAMP (1 << 12)
|
|
|
|
|
# define R128_ALPHA_COMB_SUB_DST_SRC_CLAMP (2 << 12)
|
|
|
|
|
# define R128_ALPHA_COMB_SUB_DST_SRC_NCLAMP (3 << 12)
|
|
|
|
|
# define R128_FOG_TABLE (1 << 14)
|
|
|
|
|
# define R128_SIGNED_DST_CLAMP (1 << 15)
|
|
|
|
|
# define R128_ALPHA_BLEND_SRC_ZERO (0 << 16)
|
|
|
|
|
# define R128_ALPHA_BLEND_SRC_ONE (1 << 16)
|
|
|
|
|
# define R128_ALPHA_BLEND_SRC_SRCCOLOR (2 << 16)
|
|
|
|
|
# define R128_ALPHA_BLEND_SRC_INVSRCCOLOR (3 << 16)
|
|
|
|
|
# define R128_ALPHA_BLEND_SRC_SRCALPHA (4 << 16)
|
|
|
|
|
# define R128_ALPHA_BLEND_SRC_INVSRCALPHA (5 << 16)
|
|
|
|
|
# define R128_ALPHA_BLEND_SRC_DSTALPHA (6 << 16)
|
|
|
|
|
# define R128_ALPHA_BLEND_SRC_INVDSTALPHA (7 << 16)
|
|
|
|
|
# define R128_ALPHA_BLEND_SRC_DSTCOLOR (8 << 16)
|
|
|
|
|
# define R128_ALPHA_BLEND_SRC_INVDSTCOLOR (9 << 16)
|
|
|
|
|
# define R128_ALPHA_BLEND_SRC_SAT (10 << 16)
|
|
|
|
|
# define R128_ALPHA_BLEND_SRC_BLEND (11 << 16)
|
|
|
|
|
# define R128_ALPHA_BLEND_SRC_INVBLEND (12 << 16)
|
|
|
|
|
# define R128_ALPHA_BLEND_DST_ZERO (0 << 20)
|
|
|
|
|
# define R128_ALPHA_BLEND_DST_ONE (1 << 20)
|
|
|
|
|
# define R128_ALPHA_BLEND_DST_SRCCOLOR (2 << 20)
|
|
|
|
|
# define R128_ALPHA_BLEND_DST_INVSRCCOLOR (3 << 20)
|
|
|
|
|
# define R128_ALPHA_BLEND_DST_SRCALPHA (4 << 20)
|
|
|
|
|
# define R128_ALPHA_BLEND_DST_INVSRCALPHA (5 << 20)
|
|
|
|
|
# define R128_ALPHA_BLEND_DST_DSTALPHA (6 << 20)
|
|
|
|
|
# define R128_ALPHA_BLEND_DST_INVDSTALPHA (7 << 20)
|
|
|
|
|
# define R128_ALPHA_BLEND_DST_DSTCOLOR (8 << 20)
|
|
|
|
|
# define R128_ALPHA_BLEND_DST_INVDSTCOLOR (9 << 20)
|
|
|
|
|
# define R128_ALPHA_TEST_NEVER (0 << 24)
|
|
|
|
|
# define R128_ALPHA_TEST_LESS (1 << 24)
|
|
|
|
|
# define R128_ALPHA_TEST_LESSEQUAL (2 << 24)
|
|
|
|
|
# define R128_ALPHA_TEST_EQUAL (3 << 24)
|
|
|
|
|
# define R128_ALPHA_TEST_GREATEREQUAL (4 << 24)
|
|
|
|
|
# define R128_ALPHA_TEST_GREATER (5 << 24)
|
|
|
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# define R128_ALPHA_TEST_NEQUAL (6 << 24)
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# define R128_ALPHA_TEST_ALWAYS (7 << 24)
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# define R128_COMPOSITE_SHADOW_CMP_EQUAL (0 << 28)
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# define R128_COMPOSITE_SHADOW_CMP_NEQUAL (1 << 28)
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# define R128_COMPOSITE_SHADOW (1 << 29)
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# define R128_TEX_MAP_ALPHA_IN_TEXTURE (1 << 30)
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# define R128_TEX_CACHE_LINE_SIZE_8QW (0 << 31)
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# define R128_TEX_CACHE_LINE_SIZE_4QW (1 << 31)
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#define R128_REG_SCALE_3D_DATATYPE 0x1a20
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#define R128_REG_TEX_CNTL_C 0x1c9c
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# define R128_TEX_ALPHA_EN (1 << 9)
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# define R128_TEX_CACHE_FLUSH (1 << 23)
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#define R128_REG_PRIM_TEX_CNTL_C 0x1cb0
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#define R128_REG_PRIM_TEXTURE_COMBINE_CNTL_C 0x1cb4
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#define R128_DATATYPE_C8 2
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#define R128_DATATYPE_ARGB_1555 3
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#define R128_DATATYPE_RGB_565 4
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#define R128_DATATYPE_ARGB_8888 6
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#define R128_DATATYPE_RGB_332 7
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#define R128_DATATYPE_Y8 8
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#define R128_DATATYPE_RGB_8 9
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#define R128_DATATYPE_VYUY_422 11
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#define R128_DATATYPE_YVYU_422 12
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#define R128_DATATYPE_AYUV_444 14
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#define R128_DATATYPE_ARGB_4444 15
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#define R128_PM4_NONPM4 (0 << 28)
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#define R128_PM4_192PIO (1 << 28)
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#define R128_PM4_192BM (2 << 28)
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#define R128_PM4_128PIO_64INDBM (3 << 28)
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#define R128_PM4_128BM_64INDBM (4 << 28)
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#define R128_PM4_64PIO_128INDBM (5 << 28)
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#define R128_PM4_64BM_128INDBM (6 << 28)
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#define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28)
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#define R128_PM4_64BM_64VCBM_64INDBM (8 << 28)
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#define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28)
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