c8eb20a08e
pixmaps are offscreen and don't have alpha maps. It is the last case
checked before going to software fallback
- Use the new Composite hook in the ati driver to implement acceleration of
most Composites that get done in an xcompmgr environment on r100 series
cards. It is only available when using the DRM. There are still some
corruption issues, but the DRI is still non-default and I need to get
this into version control.
556 lines
14 KiB
C
556 lines
14 KiB
C
/*
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* $Id$
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*
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* Copyright © 2003 Eric Anholt
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that
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* copyright notice and this permission notice appear in supporting
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* documentation, and that the name of Eric Anholt not be used in
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* advertising or publicity pertaining to distribution of the software without
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* specific, written prior permission. Eric Anholt makes no
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* representations about the suitability of this software for any purpose. It
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* is provided "as is" without express or implied warranty.
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*
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* ERIC ANHOLT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL ERIC ANHOLT BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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/* $Header$ */
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#ifdef HAVE_CONFIG_H
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#include <config.h>
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#endif
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#include "ati.h"
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#include "ati_reg.h"
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#include "ati_draw.h"
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#ifdef USE_DRI
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#include "radeon_common.h"
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#include "r128_common.h"
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#include "ati_sarea.h"
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#endif /* USE_DRI */
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CARD8 ATISolidRop[16] = {
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/* GXclear */ 0x00, /* 0 */
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/* GXand */ 0xa0, /* src AND dst */
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/* GXandReverse */ 0x50, /* src AND NOT dst */
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/* GXcopy */ 0xf0, /* src */
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/* GXandInverted*/ 0x0a, /* NOT src AND dst */
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/* GXnoop */ 0xaa, /* dst */
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/* GXxor */ 0x5a, /* src XOR dst */
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/* GXor */ 0xfa, /* src OR dst */
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/* GXnor */ 0x05, /* NOT src AND NOT dst */
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/* GXequiv */ 0xa5, /* NOT src XOR dst */
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/* GXinvert */ 0x55, /* NOT dst */
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/* GXorReverse */ 0xf5, /* src OR NOT dst */
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/* GXcopyInverted*/ 0x0f, /* NOT src */
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/* GXorInverted */ 0xaf, /* NOT src OR dst */
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/* GXnand */ 0x5f, /* NOT src OR NOT dst */
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/* GXset */ 0xff, /* 1 */
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};
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CARD8 ATIBltRop[16] = {
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/* GXclear */ 0x00, /* 0 */
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/* GXand */ 0x88, /* src AND dst */
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/* GXandReverse */ 0x44, /* src AND NOT dst */
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/* GXcopy */ 0xcc, /* src */
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/* GXandInverted*/ 0x22, /* NOT src AND dst */
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/* GXnoop */ 0xaa, /* dst */
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/* GXxor */ 0x66, /* src XOR dst */
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/* GXor */ 0xee, /* src OR dst */
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/* GXnor */ 0x11, /* NOT src AND NOT dst */
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/* GXequiv */ 0x99, /* NOT src XOR dst */
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/* GXinvert */ 0x55, /* NOT dst */
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/* GXorReverse */ 0xdd, /* src OR NOT dst */
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/* GXcopyInverted*/ 0x33, /* NOT src */
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/* GXorInverted */ 0xbb, /* NOT src OR dst */
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/* GXnand */ 0x77, /* NOT src OR NOT dst */
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/* GXset */ 0xff, /* 1 */
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};
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static CARD32 R128BlendOp[] = {
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/* Clear */
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R128_ALPHA_BLEND_SRC_ZERO | R128_ALPHA_BLEND_DST_ZERO,
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/* Src */
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R128_ALPHA_BLEND_SRC_ONE | R128_ALPHA_BLEND_DST_ZERO,
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/* Dst */
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R128_ALPHA_BLEND_SRC_ZERO | R128_ALPHA_BLEND_DST_ONE,
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/* Over */
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R128_ALPHA_BLEND_SRC_ONE | R128_ALPHA_BLEND_DST_INVSRCALPHA,
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/* OverReverse */
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R128_ALPHA_BLEND_SRC_INVDSTALPHA | R128_ALPHA_BLEND_DST_ONE,
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/* In */
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R128_ALPHA_BLEND_SRC_DSTALPHA | R128_ALPHA_BLEND_DST_ZERO,
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/* InReverse */
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R128_ALPHA_BLEND_SRC_ZERO | R128_ALPHA_BLEND_DST_SRCALPHA,
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/* Out */
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R128_ALPHA_BLEND_SRC_INVDSTALPHA | R128_ALPHA_BLEND_DST_ZERO,
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/* OutReverse */
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R128_ALPHA_BLEND_SRC_ZERO | R128_ALPHA_BLEND_DST_INVSRCALPHA,
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/* Atop */
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R128_ALPHA_BLEND_SRC_DSTALPHA | R128_ALPHA_BLEND_DST_INVSRCALPHA,
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/* AtopReverse */
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R128_ALPHA_BLEND_SRC_INVDSTALPHA | R128_ALPHA_BLEND_DST_SRCALPHA,
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/* Xor */
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R128_ALPHA_BLEND_SRC_INVDSTALPHA | R128_ALPHA_BLEND_DST_INVSRCALPHA,
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/* Add */
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R128_ALPHA_BLEND_SRC_ONE | R128_ALPHA_BLEND_DST_ONE,
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};
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int copydx, copydy;
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int fifo_size;
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ATIScreenInfo *accel_atis;
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int src_pitch;
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int src_offset;
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int src_bpp;
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/* If is_24bpp is set, then we are using the accelerator in 8-bit mode due
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* to it being broken for 24bpp, so coordinates have to be multiplied by 3.
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*/
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int is_24bpp;
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static void
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ATIWaitAvailMMIO(int n)
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{
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ATICardInfo *atic = accel_atis->atic;
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char *mmio = atic->reg_base;
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if (fifo_size >= n) {
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fifo_size -= n;
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return;
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}
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if (atic->is_radeon) {
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do {
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fifo_size = MMIO_IN32(mmio, RADEON_REG_RBBM_STATUS) &
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RADEON_RBBM_FIFOCNT_MASK;
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} while (fifo_size < n);
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} else {
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do {
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fifo_size = MMIO_IN32(mmio, R128_REG_GUI_STAT) & 0xfff;
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} while (fifo_size < n);
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}
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fifo_size -= n;
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}
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static void
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RadeonWaitIdle(void)
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{
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ATIScreenInfo *atis = accel_atis;
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ATICardInfo *atic = atis->atic;
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char *mmio = atic->reg_base;
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CARD32 temp;
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#ifdef USE_DRI
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if (atis->using_dma) {
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int ret;
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do {
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ret = drmCommandNone(atic->drmFd, DRM_RADEON_CP_IDLE);
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} while (ret == -EBUSY);
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if (ret != 0)
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ErrorF("Failed to idle DMA, returned %d\n", ret);
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}
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#endif /* USE_DRI */
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/* Wait for the engine to go idle */
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ATIWaitAvailMMIO(64);
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while ((MMIO_IN32(mmio, RADEON_REG_RBBM_STATUS) &
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RADEON_RBBM_ACTIVE) != 0)
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;
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/* Flush pixel cache */
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temp = MMIO_IN32(mmio, RADEON_REG_RB2D_DSTCACHE_CTLSTAT);
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temp |= RADEON_RB2D_DC_FLUSH_ALL;
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MMIO_OUT32(mmio, RADEON_REG_RB2D_DSTCACHE_CTLSTAT, temp);
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while ((MMIO_IN32(mmio, RADEON_REG_RB2D_DSTCACHE_CTLSTAT) &
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RADEON_RB2D_DC_BUSY) != 0)
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;
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}
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static void
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R128WaitIdle(void)
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{
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ATIScreenInfo *atis = accel_atis;
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ATICardInfo *atic = atis->atic;
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char *mmio = atic->reg_base;
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CARD32 temp;
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int tries;
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#ifdef USE_DRI
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if (atis->using_dma) {
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int ret;
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do {
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ret = drmCommandNone(atic->drmFd, DRM_R128_CCE_IDLE);
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} while (ret == -EBUSY);
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if (ret != 0)
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ErrorF("Failed to idle DMA, returned %d\n", ret);
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}
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#endif /* USE_DRI */
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ATIWaitAvailMMIO(64);
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tries = 1000000;
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while (tries--) {
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if ((MMIO_IN32(mmio, R128_REG_GUI_STAT) & R128_GUI_ACTIVE) == 0)
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break;
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}
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temp = MMIO_IN32(mmio, R128_REG_PC_NGUI_CTLSTAT);
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MMIO_OUT32(mmio, R128_REG_PC_NGUI_CTLSTAT, temp | 0xff);
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tries = 1000000;
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while (tries--) {
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if ((MMIO_IN32(mmio, R128_REG_PC_NGUI_CTLSTAT) & R128_PC_BUSY) !=
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R128_PC_BUSY)
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break;
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}
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}
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void
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ATIWaitIdle(void)
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{
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ATIScreenInfo *atis = accel_atis;
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ATICardInfo *atic = atis->atic;
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#ifdef USE_DRI
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/* Dispatch any accumulated commands first. */
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if (atis->using_dma && atis->indirectBuffer != NULL)
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ATIDMAFlushIndirect(0);
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#endif /* USE_DRI */
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if (atic->is_radeon)
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RadeonWaitIdle();
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else
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R128WaitIdle();
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}
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#ifdef USE_DRI
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void ATIDMAStart(ScreenPtr pScreen)
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{
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KdScreenPriv(pScreen);
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ATICardInfo(pScreenPriv);
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ATIScreenInfo(pScreenPriv);
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int ret;
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if (atic->is_radeon)
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ret = drmCommandNone(atic->drmFd, DRM_RADEON_CP_START);
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else
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ret = drmCommandNone(atic->drmFd, DRM_R128_CCE_START);
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if (ret == 0)
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atis->using_dma = TRUE;
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else
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ErrorF("%s: DMA start returned %d\n", __FUNCTION__, ret);
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}
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/* Attempts to idle the DMA engine, and stops it. Note that the ioctl is the
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* same for both R128 and Radeon, so we can just use the name of one of them.
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*/
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void ATIDMAStop(ScreenPtr pScreen)
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{
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KdScreenPriv(pScreen);
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ATICardInfo(pScreenPriv);
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ATIScreenInfo(pScreenPriv);
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drmRadeonCPStop stop;
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int ret;
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stop.flush = 1;
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stop.idle = 1;
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ret = drmCommandWrite(atic->drmFd, DRM_RADEON_CP_STOP, &stop,
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sizeof(drmRadeonCPStop));
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if (ret != 0 && errno == EBUSY) {
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ErrorF("Failed to idle the DMA engine\n");
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stop.idle = 0;
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ret = drmCommandWrite(atic->drmFd, DRM_RADEON_CP_STOP, &stop,
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sizeof(drmRadeonCPStop));
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}
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atis->using_dma = FALSE;
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}
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/* The R128 and Radeon Indirect ioctls differ only in the ioctl number */
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void ATIDMADispatchIndirect(Bool discard)
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{
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ATIScreenInfo *atis = accel_atis;
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ATICardInfo *atic = atis->atic;
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drmBufPtr buffer = atis->indirectBuffer;
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drmR128Indirect indirect;
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int cmd;
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indirect.idx = buffer->idx;
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indirect.start = atis->indirectStart;
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indirect.end = buffer->used;
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indirect.discard = discard;
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cmd = atic->is_radeon ? DRM_RADEON_INDIRECT : DRM_R128_INDIRECT;
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drmCommandWriteRead(atic->drmFd, cmd, &indirect,
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sizeof(drmR128Indirect));
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}
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/* Flush the indirect buffer to the kernel for submission to the card */
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void ATIDMAFlushIndirect(Bool discard)
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{
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ATIScreenInfo *atis = accel_atis;
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drmBufPtr buffer = atis->indirectBuffer;
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if (buffer == NULL)
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return;
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if ((atis->indirectStart == buffer->used) && !discard)
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return;
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ATIDMADispatchIndirect(discard);
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if (discard) {
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atis->indirectBuffer = ATIDMAGetBuffer();
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atis->indirectStart = 0;
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} else {
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/* Start on a double word boundary */
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atis->indirectStart = buffer->used = (buffer->used + 7) & ~7;
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}
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}
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/* Get an indirect buffer for the DMA 2D acceleration commands */
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drmBufPtr ATIDMAGetBuffer()
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{
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ATIScreenInfo *atis = accel_atis;
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ATICardInfo *atic = atis->atic;
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drmDMAReq dma;
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drmBufPtr buf = NULL;
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int indx = 0;
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int size = 0;
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int ret;
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dma.context = atis->serverContext;
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dma.send_count = 0;
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dma.send_list = NULL;
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dma.send_sizes = NULL;
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dma.flags = 0;
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dma.request_count = 1;
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if (atis->atic->is_radeon)
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dma.request_size = RADEON_BUFFER_SIZE;
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else
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dma.request_size = R128_BUFFER_SIZE;
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dma.request_list = &indx;
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dma.request_sizes = &size;
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dma.granted_count = 0;
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do {
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ret = drmDMA(atic->drmFd, &dma);
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} while (ret != 0);
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buf = &atis->buffers->list[indx];
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buf->used = 0;
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return buf;
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}
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/* The hardware has a cache on the memory controller for writes to the
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* destination, which I guess is separate for 2d and 3d. So, when switching
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* between 2d and 3d you need to wait for idle and for the cache to clean.
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*/
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void
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RadeonSwitchTo2D(void)
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{
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ATIScreenInfo *atis = accel_atis;
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RING_LOCALS;
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BEGIN_RING(2);
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OUT_RING(DMA_PACKET0(RADEON_REG_WAIT_UNTIL, 0));
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OUT_RING(RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
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ADVANCE_RING();
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}
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void
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RadeonSwitchTo3D(void)
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{
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ATIScreenInfo *atis = accel_atis;
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RING_LOCALS;
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BEGIN_RING(2);
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OUT_RING(DMA_PACKET0(RADEON_REG_WAIT_UNTIL, 0));
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OUT_RING(RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN);
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ADVANCE_RING();
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}
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#endif /* USE_DRI */
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static Bool
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R128GetDatatypePict(CARD32 format, CARD32 *type)
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{
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switch (format) {
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case PICT_a8r8g8b8:
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*type = R128_DATATYPE_ARGB_8888;
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return TRUE;
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case PICT_r5g6b5:
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*type = R128_DATATYPE_RGB_565;
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return TRUE;
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}
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ErrorF ("Unsupported format: %x\n", format);
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return FALSE;
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}
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/* Assumes that depth 15 and 16 can be used as depth 16, which is okay since we
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* require src and dest datatypes to be equal.
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*/
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static Bool
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ATIGetDatatypeBpp(int bpp, CARD32 *type)
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{
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is_24bpp = FALSE;
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switch (bpp) {
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case 8:
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*type = R128_DATATYPE_C8;
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return TRUE;
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case 16:
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*type = R128_DATATYPE_RGB_565;
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return TRUE;
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case 24:
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*type = R128_DATATYPE_C8;
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is_24bpp = TRUE;
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return TRUE;
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case 32:
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*type = R128_DATATYPE_ARGB_8888;
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return TRUE;
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default:
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ErrorF("Unsupported bpp: %x\n", bpp);
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return FALSE;
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}
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}
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#ifdef USE_DRI
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#define USE_DMA
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#include "ati_drawtmp.h"
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#include "r128_blendtmp.h"
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#endif /* USE_DRI */
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#undef USE_DMA
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#include "ati_drawtmp.h"
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#include "r128_blendtmp.h"
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static void
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ATIDoneSolid(void)
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{
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}
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static void
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ATIDoneCopy(void)
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{
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}
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Bool
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ATIDrawInit(ScreenPtr pScreen)
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{
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KdScreenPriv(pScreen);
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ATIScreenInfo(pScreenPriv);
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ATICardInfo(pScreenPriv);
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ErrorF("Screen: %d/%d depth/bpp\n", pScreenPriv->screen->fb[0].depth,
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pScreenPriv->screen->fb[0].bitsPerPixel);
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#ifdef USE_DRI
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if (atis->using_dri)
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ATIDMAStart(pScreen);
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else {
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if (ATIDRIScreenInit(pScreen))
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atis->using_dri = TRUE;
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}
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#endif /* USE_DRI */
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memset(&atis->kaa, 0, sizeof(KaaScreenInfoRec));
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#ifdef USE_DRI
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if (atis->using_dma) {
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atis->kaa.PrepareSolid = ATIPrepareSolidDMA;
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atis->kaa.Solid = ATISolidDMA;
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atis->kaa.PrepareCopy = ATIPrepareCopyDMA;
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atis->kaa.Copy = ATICopyDMA;
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if (!atic->is_radeon) {
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atis->kaa.PrepareBlend = R128PrepareBlendDMA;
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atis->kaa.Blend = R128BlendDMA;
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atis->kaa.DoneBlend = R128DoneBlendDMA;
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} else if (!atic->is_r200) {
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atis->kaa.PrepareBlend = RadeonPrepareBlend;
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atis->kaa.Blend = RadeonBlend;
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atis->kaa.DoneBlend = RadeonDoneBlend;
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atis->kaa.PrepareComposite = RadeonPrepareComposite;
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atis->kaa.Composite = RadeonComposite;
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atis->kaa.DoneComposite = RadeonDoneComposite;
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}
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} else {
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#else
|
|
{
|
|
#endif /* USE_DRI */
|
|
atis->kaa.PrepareSolid = ATIPrepareSolidMMIO;
|
|
atis->kaa.Solid = ATISolidMMIO;
|
|
atis->kaa.PrepareCopy = ATIPrepareCopyMMIO;
|
|
atis->kaa.Copy = ATICopyMMIO;
|
|
if (!atic->is_radeon) {
|
|
atis->kaa.PrepareBlend = R128PrepareBlendMMIO;
|
|
atis->kaa.Blend = R128BlendMMIO;
|
|
atis->kaa.DoneBlend = R128DoneBlendMMIO;
|
|
}
|
|
}
|
|
atis->kaa.DoneSolid = ATIDoneSolid;
|
|
atis->kaa.DoneCopy = ATIDoneCopy;
|
|
atis->kaa.flags = KAA_OFFSCREEN_PIXMAPS;
|
|
if (atic->is_radeon) {
|
|
atis->kaa.offscreenByteAlign = 1024;
|
|
atis->kaa.offscreenPitch = 1024;
|
|
} else {
|
|
atis->kaa.offscreenByteAlign = 32;
|
|
/* Pitch alignment is in sets of 8 pixels, and we need to cover
|
|
* 32bpp, so 32 bytes.
|
|
*/
|
|
atis->kaa.offscreenPitch = 32;
|
|
}
|
|
if (!kaaDrawInit(pScreen, &atis->kaa))
|
|
return FALSE;
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
void
|
|
ATIDrawEnable(ScreenPtr pScreen)
|
|
{
|
|
KdMarkSync(pScreen);
|
|
}
|
|
|
|
void
|
|
ATIDrawDisable(ScreenPtr pScreen)
|
|
{
|
|
}
|
|
|
|
void
|
|
ATIDrawFini(ScreenPtr pScreen)
|
|
{
|
|
#ifdef USE_DRI
|
|
KdScreenPriv(pScreen);
|
|
ATIScreenInfo(pScreenPriv);
|
|
|
|
if (atis->using_dma)
|
|
ATIDMAStop(pScreen);
|
|
|
|
if (atis->using_dri)
|
|
ATIDRICloseScreen(pScreen);
|
|
#endif /* USE_DRI */
|
|
|
|
kaaDrawFini(pScreen);
|
|
}
|
|
|
|
void
|
|
ATIDrawSync(ScreenPtr pScreen)
|
|
{
|
|
KdScreenPriv(pScreen);
|
|
ATIScreenInfo(pScreenPriv);
|
|
|
|
accel_atis = atis;
|
|
|
|
ATIWaitIdle();
|
|
}
|